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never stop thinking. hys72t128001hf[n/a]?3.7?a hys72t256021hf[n/a]?3.7?a 240-pin fully-buffered ddr2 sdram modules ddr2 sdram fb-dimm sdram rohs compliant green product high-speed differential point-to-point link interface at 1.5 v data sheet, rev. 1.10, nov. 2005 memory products
edition 2005-11 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: mp_a4_s_rev321 / 3 / 2005-10-05 hys72t128001hf[n/a]?3.7?a hys72t256021hf[n/a]?3.7?a revision history: 2005-11, rev. 1.10 previous version: 1.01 page subjects (major cha nges since last revision) 7 updated table 1 ?performance for ddr2-533? on page 7 8 updated table 2 ?ordering information (pb-free components and assembly)? on page 8 8 added table 3 ?address format? on page 8 8 added table 4 ?components on modules? on page 8 23 updated table 6 ?electrical characteristics? on page 23 51 updated ?spd codes? on page 51 62 updated figure 18 ?package outline l-dim-240-21? on page 62 63 updated figure 19 ?package outline l-dim-240-22? on page 63 we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 4 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 fb-dimm input/output functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 jedec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 advanced memory buffer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 advanced memory buffer functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 high-speed differential point-to -point link (at 1.5 v) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 5.4.1 ddr2 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.2 smbus slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.3 channel latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.4 peak theoretical channel throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 high-speed differential point-to-point link interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 differential signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.1 transition density in transmitted signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.2 jitter and bit error rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.3 de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.4 electrical idle (ei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.5 reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 high speed serial link reference clocks (sck, sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 spread spectrum clocking (ssc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 reference clock input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5 differential transmitter output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.6 differential receiver input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6.1 receiver input compliance eye specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 channel initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1.1 inband control ?signals? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 channel initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2.1 firmware transition control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2.2 amb internal state variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2.3 disable state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2.4 training state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2.5 testing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2.6 polling state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2.7 config state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 channel protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 southbound frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table of contents
data sheet 5 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram table of contents 9.1.1 normal southbound frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.2 fail-over southbound frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.3 command frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.3.1 command frame with data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.3.2 command+wdata frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.4 southbound commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.4.1 dram commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.4.2 channel commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.4.3 cke control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.4.4 soft channel reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.4.5 sync command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4.6 nop frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4.7 command delivery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4.8 concurrent command delivery rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4.9 command encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 northbound crc m odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.1 northbound idle frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.2 northbound alert frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3 northbound data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3.1 14-bit lane northbound data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3.2 13-bit lane fail-over northbound data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3.3 13-bit lane northbound data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3.4 13-bit lane fail-over northbound data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.3.5 12-bit lane northbound data frame (non-ecc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.3.6 northbound register data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.3.7 northbound status frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 dram memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.1 read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.2 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.2.1 write data fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.3 simultaneous read and write data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.4 dram bus segment restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 reliability, availabili ty and serv iceability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 example error flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.1 command error flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.2 write data error flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.3 read error flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 overview of error protection, detection, correction, and logging . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.4 error protection and detection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4.1 crc logic used on normal southbound fr ames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4.2 fail-over southbound frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4.3 write and read data ecc error protec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5 southbound error handling at the amb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5.1 exiting command error state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6 northbound error handling at the amb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.7 error logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.8 fail-over mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.8.1 fail-over mode operation on southbound lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.8.2 fail-over mode operation on northbound lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.9 amb pass-through functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram table of contents data sheet 6 rev. 1.10, 2005-11 02182005-fiin-vwua 10.10 memory initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.11 thermal trip sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13 ddr2 nomencature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
data sheet 7 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram overview 1overview this chapter describes the main c haracteristics of the 240-pin fully -buffered ddr2 sdram modules product family. 1.1 features ? 240-pin fully-buffered ecc dual-in-line ddr2 sdram module for pc, workstation and server main memo ry applications. ? one rank 128mb x 72 and two ranks 256mb x 72 memory array. ? jedec standard double data rate 2 synchronous drams (ddr2 sdrams) with 1.8 v ( 0.1 v) power supply. ? built with 1gb ddr2 sdra ms in 68-ball chipsize packages. ? re-drive and re-sync of all address, command, clock and data signals using amb (advanced memory buffer). ? high-speed differential point-to-point link interface at 1.5 v (jedec standard pending). ? host interface and amb component industry standard compliant. ? supports smbus protocol interface for access to the amb configuration registers. ? detects errors on the channel and reports them to the host memory controller. ? automatic ddr2 dram bus calibration. ? automatic channel calibration. ? full host control of the ddr2 drams. ? over-temperature detection and alert. ? hot add-on and hot remove capability. ? mbist and ibist test functions. ? transparent mode for dram test support. ? low profile: 133.35mm x 30,35mm ? 240 pin gold plated card connector with 1.00mm contact centers (jedec standard pending). ? based on jedec standard reference card designs (jedec standard pending). ? spd (serial presence detect) with 256 byte serial e 2 prom.performance: ? rohs compliant products 1) 1.2 description this document describes the electrical and mechanical features of infineon?s 240- pin, pc2-4200f ecc type, fully buffered double-data-rate two synchronous dram dual in-line memo ry modules (ddr2 sdram fb-dimms). fully buffer ed dimms use commodity drams isolated from the memory channel behind a buffer on the dimm. they are intended for use as main memory when installed in systems such as servers and workstations. pc2-4200 refers to the dimm naming convention indicating t he ddr2 sdrams running at 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers. table 1 performanc e for ddr2-533 product type speed code ?3.7 units speed grade pc2?4200 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram overview data sheet 8 rev. 1.10, 2005-11 02182005-fiin-vwua 266 mhz clock speed and offering 4200 mb/s peak bandwidth. fb-dimm features a novel architecture including the advanced memory buffer. this single chip component, located in the center of each dimm, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the ddr2 sdrams including data in- and output. the amb communicates with the host controller and / or the adjacent dimms on a system board using an industry standard high-speed differential point- to-point link interface at 1.5 v. the advanced memory buffer also allows buffering of memory traffic to support la rge memory capacities. all memory control for the dr am resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. the advanced memory buffer interface is responsible for handling channel and memory requests to and from the local dimm and for forwarding requests to other dimms on the memory channel. fully buffered dimm provides a high memory bandwidth, large capacity channel soluti on that has a narrow host interface. the maximum memory capacity is 288 ddr2 sdram devices per channel or 8 dimms. table 2 ordering information (pb-free components and assembly) type & partnumber 1) 1) all product types end with a place code, designating the s ilicon die revision. example: hys 72t64000hf-3.7-a, indicating rev. a dice are used for ddr2 sdram components. to learn more on infineon ddr2 module and component nomenclature see section 8 of this datasheet. compliance code 2) 2) the compliance code is printed on the module label and descr ibes the speed grade, e.g. ?pc2-4200f-444-10-c?, where 4200f means fully buffered dimm with 4.26 gb/sec module bandwidth and ?444-10? means cas latency = 4, t rcd latency = 4 and t rp latency = 4 using jedec spd revision 1.0 and assembled on raw card ?c?. description sdram technology pc2-4200f (ddr2-533): hys72t128001hfn?3.7?a pc2-4200f?444?10?a one rank 1 gb fb?dimm 1gbit (x8) hys72t128001hfa?3.7?a pc2-4200f?444?10?a one rank 1 gb fb?dimm 1gbit (x8) hys72t256021hfn?3.7?a pc2-4200f?444?10?b two ranks 2 gb fb?dimm 1gbit (x8) hys72t256021hfa?3.7?a pc2-4200f?444?10?b two ranks 2 gb fb?dimm 1gbit (x8) table 3 address format dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 1 gb 128m 72 1 ecc 9 14/3/10 a 2 gb 256m 72 2 ecc 18 14/3/10 b table 4 components on modules 1) 1) for a detailed description of all functi onalities of the dram components on th ese modules see the component datasheet. product type dram components 2) 2) green product dram density dram organisation hys72t128001hf hyb18t1g800af 1 gbit 128m 8 hys72t256021hf hyb18t1g800af 1 gbit 128m 8
data sheet 9 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration 2 pin configuration the pin configuration of the ddr2 s dram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 7 and table 6 respectively. the pin numbering is depicted in figure 1 . table 5 pin configuration of fb-dimm pin# name pin type buffer type function clock signals 228 sck i hsdl_15 system clock input, positive line 229 sck i hsdl_15 system clock input, negative line control signals 17 reset i lv-cmos amb reset signal northbound 22 pn0 o hsdl_15 primary northbound data, positive lines 25 pn1 o hsdl_15 28 pn2 o hsdl_15 31 pn3 o hsdl_15 34 pn4 o hsdl_15 37 pn5 o hsdl_15 51 pn6 o hsdl_15 54 pn7 o hsdl_15 57 pn8 o hsdl_15 60 pn9 o hsdl_15 63 pn10 o hsdl_15 66 pn11 o hsdl_15 48 pn12 o hsdl_15 40 pn13 o hsdl_15 23 pn0 o hsdl_15 primary northbound data, negative lines 26 pn1 o hsdl_15 29 pn2 o hsdl_15 32 pn3 o hsdl_15 35 pn4 o hsdl_15 38 pn5 o hsdl_15 52 pn6 o hsdl_15 55 pn7 o hsdl_15 58 pn8 o hsdl_15 61 pn9 o hsdl_15 64 pn10 o hsdl_15 67 pn11 o hsdl_15 49 pn12 o hsdl_15 41 pn13 o hsdl_15
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration data sheet 10 rev. 1.10, 2005-11 02182005-fiin-vwua 142 sn0 i hsdl_15 secondary northbound data, positive lines 145 sn1 i hsdl_15 148 sn2 i hsdl_15 151 sn3 i hsdl_15 154 sn4 i hsdl_15 157 sn5 i hsdl_15 171 sn6 i hsdl_15 174 sn7 i hsdl_15 secondary northbound data, positive lines 177 sn8 i hsdl_15 180 sn9 i hsdl_15 183 sn10 i hsdl_15 186 sn11 i hsdl_15 168 sn12 i hsdl_15 160 sn13 i hsdl_15 143 sn0 i hsdl_15 secondary northbound data, negative lines 146 sn1 i hsdl_15 149 sn2 i hsdl_15 152 sn3 i hsdl_15 155 sn4 i hsdl_15 158 sn5 i hsdl_15 172 sn6 i hsdl_15 175 sn7 i hsdl_15 178 sn8 i hsdl_15 181 sn9 i hsdl_15 184 sn10 i hsdl_15 187 sn11 i hsdl_15 169 sn12 i hsdl_15 161 sn13 i hsdl_15 southbound 70 ps0 i hsdl_15 primary southbound data, positive lines 73 ps1 i hsdl_15 76 ps2 i hsdl_15 79 ps3 i hsdl_15 82 ps4 i hsdl_15 93 ps5 i hsdl_15 96 ps6 i hsdl_15 99 ps7 i hsdl_15 102 ps8 i hsdl_15 90 ps9 i hsdl_15 table 5 pin configuration of fb-dimm (cont?d) pin# name pin type buffer type function
data sheet 11 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration 71 ps0 i hsdl_15 primary southbound data, negative lines 74 ps1 i hsdl_15 77 ps2 i hsdl_15 80 ps3 i hsdl_15 83 ps4 i hsdl_15 94 ps5 i hsdl_15 97 ps6 i hsdl_15 100 ps7 i hsdl_15 103 ps8 i hsdl_15 91 ps9 i hsdl_15 190 ss0 o hsdl_15 secondary southbound data, positive lines 193 ss1 o hsdl_15 196 ss2 o hsdl_15 199 ss3 o hsdl_15 202 ss4 o hsdl_15 213 ss5 o hsdl_15 secondary southbound data, positive lines 216 ss6 o hsdl_15 219 ss7 o hsdl_15 222 ss8 o hsdl_15 210 ss9 o hsdl_15 191 ss0 o hsdl_15 secondary southbound data, negative lines 194 ss1 o hsdl_15 197 ss2 o hsdl_15 200 ss3 o hsdl_15 203 ss4 o hsdl_15 214 ss5 o hsdl_15 217 ss6 o hsdl_15 220 ss7 o hsdl_15 223 ss8 o hsdl_15 211 ss9 o hsdl_15 eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 118 sa2 i cmos power supplies 238 v ddspd pwr ? eeprom power supply 9,10,12,13,129,130,132,133 v cc pwr ? amb core power / channel interface power table 5 pin configuration of fb-dimm (cont?d) pin# name pin type buffer type function
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration data sheet 12 rev. 1.10, 2005-11 02182005-fiin-vwua 15,117,135,237 v tt pwr ? address/command/clock termination power 1,2,3,5,6,7,108, 109,111,112,113, 115,116,121,122,123,125,126, 127,231,232,233,235,236 v dd pwr ? power supply 4,8,11,14,18,21, 24,27,30,33,36, 39,42,43,46,47,50 ,53,56,59,62, 65,68,69,72,75,78 ,81,84,85,88, 89,92,95,98,101,104,107,110, 114,124,128,131,134,138,141, 144,147,150,153,156,159,162, 163,166,167,170,173,176,179, 182,185,188,189,192,195,198, 201,204,205,208,209,212,215, 218,221,224,227,230,234 v ss gnd ? ground plane other pins 19,20,44,45,86, 87,105,106,139, 140,164,165,206,207,225,226 nc nc ? not connected pins not connected on infineon fb- dimm?s 136 vid0 ? ? voltage id note: these pins must be unconnected for ddr2-based fully buffered dimms vid[0] is v dd value: open = 1.8 v, gnd = 1.5 v; vid[1] is v cc value: open = 1.5 v, gnd = 1.2 v 16 vid1 ? ? 137 test ai ? vref note: pin must be unconnected for normal operation table 6 abbreviations for buffer type abbreviation description hsdl_15 high-speed differential point-to -point link interface at 1.5 v lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin ha s 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 5 pin configuration of fb-dimm (cont?d) pin# name pin type buffer type function
data sheet 13 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration table 7 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram pin configuration data sheet 14 rev. 1.10, 2005-11 02182005-fiin-vwua figure 1 pin configuration for fbdimm (240 pin) 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 # # 6 3 3 6 # # 6 4 4 2 % 3 % 4 . # 6 $ $ 6 3 3 6 $ $ 6 3 3 6 # # 6 # # 6 3 3 6 ) $ 6 3 3 . # 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 . # 6 3 3 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 3 6 3 3 0 3 0 3 6 3 3 0 3 0 3 6 3 3 . # 6 3 3 0 3 6 3 3 0 3 0 3 6 3 3 0 3 0 3 6 3 3 . # 6 $ $ 6 3 3 6 $ $ 6 3 3 6 $ $ 3 ! 3 # , 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 6 3 3 . # 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 0 . 6 3 3 0 . 6 3 3 0 3 0 3 6 3 3 0 3 0 3 6 3 3 0 3 6 3 3 . # 6 3 3 0 3 0 3 6 3 3 0 3 0 3 6 3 3 0 3 . # 6 3 3 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 4 4 3 $! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 # # 6 3 3 6 # # 6 4 4 4 % 3 4 . # 6 $ $ 6 3 3 6 $ $ 6 3 3 6 # # 6 # # 6 3 3 6 ) $ 6 3 3 . # 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 . # 6 3 3 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 3 6 3 3 3 3 3 3 6 3 3 3 3 3 3 6 3 3 . # 6 3 3 3 3 6 3 3 3 3 3 3 6 3 3 3 3 3 3 6 3 3 . # 3 # + 6 3 3 6 $ $ 6 3 3 6 $ $ 6 $ $ 3 0 $ 3 ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 6 3 3 . # 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 3 . 6 3 3 3 . 6 3 3 3 3 3 3 6 3 3 3 3 3 3 6 3 3 3 3 6 3 3 . # 6 3 3 3 3 3 3 6 3 3 3 3 3 3 6 3 3 3 3 . # 6 3 3 3 # + 6 $ $ 6 $ $ 6 $ $ 6 4 4 3 ! & 2 / . 4 3 ) $ % " ! # + 3 ) $ % - 0 0 4
data sheet 15 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram fb-dimm input/output functional description 3 fb-dimm input/output functional description table 8 fb-dimm input/output functional description symbol type polarity function channel signals sck, sck input differential system clock input pn[13:0], pn[13:0] output differential primary northbound data ps[9:0], ps[9:0] input differential primary southbound data sn[13:0], sn[13:0] input differential secondary northbound data ss[9:0], ss[9:0] output differential secondary southbound data smb bus signals sa[2:0] input ? spd address, also used to select the dimm number in the amb sda i/o ? spd data. a resistor must be connected from the sda bus line to vddspd on the system planar to act as a pull-up. scl input ? spd clock miscellaneous signals reset input active low amb reset signal vid[1:0] input ? voltage id. both pins shall be nc in case of v dd =1.8v, v cc =1.5v test analog + 0.9 v dram v ref margin test. do not conne ct on the system planar. power / ground v dd supply + 1.8 v ddr2 dram power v cc supply + 1.5 v amb core power v ddspd supply + 3.3 v spd power
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram block diagrams data sheet 16 rev. 1.10, 2005-11 02182005-fiin-vwua 4 block diagrams figure 2 block diagram raw card a fb-dimm ecc (x72, 1rank, x8) notes 1. dq to i/o wiring may be changed within a byte 2. there are two physical copies of each address, command, control, clock 3. all address, command, control, clock have termination resitors to v tt - 0 " 4 $ $ $ $ $ $ $ $1 3 $1 3 $ 1 3 # " # " # " # " # " # " # " # " $ $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $1 3 $ 1 $ 1 $1 $1 $1 $1 $1 $1 $ 1 3 $ 1 3 $1 3 $1 $1 $1 $1 $1 $1 $1 $1 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / #3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / #3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / #3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / #3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 ! - " 3 # + % / $ 4 " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + # + # 3 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ " ! " ! n 3 $2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + # + 3 $ 2 ! - $ $ 3 . 3 . 3 . 3 . 3 3 3 3 3 3 3 3 4 e rm i n a t o r s ! - " 6 $ $ 3 0 $ ! - " 6 $ $ 6 $ $ 1 3 $ 2! - s $ $ ! - " 6 2 % & 3 $ 2! - s $ $ 6 3 3 3 $2 ! - s $ $ 6 4 4 6 # # 6 $ $ 3 0 $ 6 $$ 6 $ $ 1 6 2% & 6 3 3 $ $ 1 3 $ 1 3 $1 3 $1 $1 $1 $1 $1 $1 $1 $1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 $ 1 # " # " $ 1 3 $ 1 3 $ 1 3 $ 1 3 3 # , 3 $! 3 ! 3 ! 2 % 3 % 4 3 # + 3 #+ 0 . 0 . 0 . 0 . 0 3 0 3 0 3 0 3
data sheet 17 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram block diagrams figure 3 block diagram raw card b fb-dimm ecc (x72, 2ranks, x8) notes 1. dq to i/o wiring may be changed within a byte 2. there are two physical copies of each address, command, control and clock 3. all address, command, control, clock have termination resitors to v tt 4. - 0 " 4 $ $ $ $ $ $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 # 3 $ 1 3 $ 1 3 $ - 2 $1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 # 3 $ 1 3 $ 1 3 $ - 2 $1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 3 $ $ $ $1 3 $1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $1 3 $1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $1 3 $1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ $1 3 $1 3 $ 1 3 # " # " # " # " # " # " # " # " $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ ! - " 3 # + % 3 # + % / $ 4 " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + #+ # 3 3 $ 2! - s $ $ # + % 3 $ 2 ! - s $ $ # 3 3 $ 2! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + # + 3 $ 2 ! - $ $ $ 1 $ 1 #" # " $ 1 3 $ 1 3 $ 1 3 $ 1 3 3 # , 3 $ ! 3 ! 3 ! 2 % 3 % 4 3 # + 3 # + 0 . 0 . 0 . 0 . 0 3 0 3 0 3 0 3 3 . 3 . 3 . 3 . 3 3 3 3 3 3 3 3 6 4 4 6 # # 6 $ $ 3 0 $ 6 3 3 4 e r m i n a t o r s ! - " 6 $ $ 3 0 $ ! - " 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ ! - " 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2! - s $ $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram jedec data sheet 18 rev. 1.10, 2005-11 02182005-fiin-vwua 5jedec 5.1 advanced memory buffer overview the advanced memory buffer (amb) reference design complies with the fb-dimm architecture and protocol specification.the amb block diagram is depicted in figure 4 . 5.2 advanced memory buffer functionality the advanced memory buffe r will perform the following fb-dimm channel functions: ? supports channel initialization procedures as defined in the initializatio n chapter of the fb-dimm architecture and protocol specification to align the clocks and the frame boundaries, verify channel connectivity, and identify amb dimm position. ? supports the forwarding of southbound and northbound frames, servicing requests directed to a specific amb or dimm, as defined in the protocol chapter, and merging the return data into the northbound frames. ? if the amb resides on the last dimm in the channel, the amb initializes northbound frames. ? detects errors on the channel and reports them to the host memory controller. ? support the fb-dimm configuration register set as defined in the register chapters. ? acts as dram memory buffer for all read, write, and configuration accesses addressed to the dimm. ? provides a read buffer fifo and a write buffer fifo. ? supports an smbus protocol interface for access to the amb configuration registers. ? provides logic to support membist and ibist design for test functions. ? provides a register interface for the thermal sensor and status indicator. ? functions as a repeater to extend the maximum length of fb-dimm links. transparent mode for dram test support in this mode, the advanced memory buffer will provide lower speed tester access to dram pins through the fb-dimm i/o pins. this allows the tester to send an arbitrary test pattern to the drams. transparent mode only supports a maximum dram frequency equivalent to ddr2 400. transparent mode functionality: ? reconfigures fb-dimm inputs from differential high speed link receivers to two single ended lower speed receivers (~200 mhz) ? these inputs directly control ddr2 command/address and input data that is replicated to all drams ? uses low speed direct drive fb-dimm outputs to bypass high speed parallel/serial circuitry and provide test results back to tester ddr2 sdram interface ? supports ddr2 at speeds of 533, 667 mt/s ? supports 512mb devices in x4 and x8 configurations ? 72-bit ddr2 sdram memory array
data sheet 19 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram jedec figure 4 block diagram advanced memory buffer fbdimm ecc note: figure is a conceptual block diagram of the adva nced memory bufferis data flow and clock domains. - 0 " 4 . o r t h b o u n d $a t a / u t .o r t h b o u n d $ a t a ) n $ a t a - e rg e $ 8 2 e s y n c h 0 ) 3 / 2 % 4 i m e x x x x x x f a i l o v e r - 5 8 , i n k ) n i t 3 - a n d # o n t r o l a n d # 3 2 s ) " )3 4 3 y n c ) d l e 0 a t t e r n ' e n e r a to r . " , ! ) " u f f e r $ a t a # 2# ' e n 2 e a d & ) & / 3 - b u s # o n t r o l l e r 3 - " 5 3 , ! ) # o n t r o l l e r $ 2 ! - i n t e r f a c e $ 2 ! - # l o c k $ 2 ! - # l o c k $ 2 ! - ! d d re s s # o m m a n d $ 2 ! - ! d d re s s # o m m a n d $ 2 ! - $ a t a 3 t ro b s - 5 8 - 5 8 # - $ / u t $ a t a / u t $ a t a ) n % x t e r n a l - % - " ) 3 4 $ $ 2 # a l i b r a t i o n 7 r i t e $ a t a & ) & / $ $ 2 3 t a t e # o n t r o l l e r a n d # 3 2 s #o r e # o n t ro l l e r a n d # 3 2 s # o m m a n d $e c o d e r # 2# # h e c k $2 ! - # m d , ! ) , o g i c 3 o u t h b o u n d $ a t a / u t 3 o u t h b o u n d $ a t a ) n x x $ a t a - e r g e $ 8 2 e s y n c h 0 ) 3 / 2 % 4 i m e x x , i n k ) n i t 3 - a n d # o n t r o l a n d # 3 2 s f a i l o v e r ) " )3 4 - 5 8 ) n i t p a t t e r n s 4 h e r m a l 3 e n s o r x 2 e s e t # o n t ro l 0 , , 2 e s e t 2e f # l o c k x
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram jedec data sheet 20 rev. 1.10, 2005-11 02182005-fiin-vwua 5.3 interfaces figure 5 illustrates the advanced memory buffer and all of its interfaces. they consist of two fb-dimm links, one ddr2 channel and an smbus interface. each fb- dimm link connects the advanc ed memory buffer to a host memory controller or an adjacent fb-dimm. the ddr2 channel supports dire ct connection to the ddr2 sdrams on a fully buffered dimm. figure 5 block diagram advanced memory buffer interface interface topology the fb-dimm channel uses a daisy-chain topology to provide expansion from a single dimm per channel to up to 8 dimms per channel. the host sends data on the southbound link to the first dimm where it is received and redriven to the second dimm. on the southbound data path each dimm receives the data and again re- drives the data to the next dimm until the last dimm receives the data. the last dimm in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). on the northbound data path each dimm receives the data and re-drives the data to the next dimm until the host is reached. figure 6 block diagram fbdimm channel soutbound and northbound paths - 0 " 4 ! - " - e m o r y ) n t e r f a c e 0 r i m a r y o r ( o s t $ i r e c t i o n 3 e c o n d a r y o r t o o p t i o n a l n e x t & " $ . " & " $ o u t , i n k 3 " & " $ i n , i n k . " & " $ i n , i n k 3 " & " $ o u t , i n k 3 - " - 0 " 4 ! - " ! - " ! - " ! - " ( o s t n c n c 3 o u t h b o u n d . o u r t h b o u n d
data sheet 21 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram jedec 5.4 high-speed differential point-to -point link (at 1.5 v) interfaces the advanced memory buffer supports one fb-dimm channel consisting of two bidirectional link interfaces using highspeed differential point-to-point electrical signaling. the southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent dimm in the host direction. the southbound output link forwards this same data to the next fb-dimm. the northbound input link is 14 lanes wide and ca rries read return data or status information from the next fb-dimm in the chain back towards the host. the northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. data and commands sent to the drams travel southbound on 10 primary differential signal line pairs. data received from the drams and status information travel northbound on 14 primary differential pairs. data and commands sent to the adjacent dimm upstream are repeated and travel further southbound on 10 secondary differential pairs. data and status information received from the adjacent dimm upstream travel further northbound on 14 secondary differential pairs. 5.4.1 ddr2 channel the ddr2 channel on the advanced memory buffer supports direct connection to ddr2 sdrams. the ddr2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. there are two copies of address and command signals to support dimm routing and electrical requirements. four transfer bursts are driven on the data and check-bit lines at 800 mhz. propagation delays between read data/check-bit strobe lanes on a given channel can differ. each strobe can be calibrated by hardware state machines using write/read trial and error. hardware aligns the read data and check-bits to a single core clock. the advanced memory buffer provides four copies of the command clock phase references (clk[3:0]) and write data/check-bit strobes (dqss) for each dram nibble. 5.4.2 smbus slave interface the advanced memory buffer supports an smbus interface to allow system access to configuration registers independent of the fb-dimm link. the advanced memory buffer will never be a master on the smbus, only a slave. serial smbus data transfer is supported at 100 khz. sm bus access to the advanced memory buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. it is also required for diagnostic support when the link is down. the smbus address straps located on the dimm connector are used by the unique id. 5.4.3 channel latency fb-dimm channel latency is measured from the time a read request is driven on the fb-dimm channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller. when not using the variab le read latency capability, the latency for a specific dimm on a channel is always equal to the latency for any other dimm on that channel. however, the latency for each dimm in a specific configuration with some number of dimms installed may not be equal to the latency for each fb- dimm in a configuration with some different number of dimms installed. as more dimms are added to the channel, additional latency is required to read from each dimm on the channel. because the channel is based on the point-to-point interconnection of buffer components between dimms, memory requests are required to travel through n-1 buffers before reaching the nth buffer. the result is that a 4 dimm channel configuration will have gr eater idle read latency compared to a 1 dimm channel configuration. the variable read latency capability can be used to reduce latency for dimms closer to the host. the idle latencies listed in this section are representative of what might be achieved in typical amb designs. actual implementations with latenc ies less than the values listed will have higher applicat ion performa nce and vice versa.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram jedec data sheet 22 rev. 1.10, 2005-11 02182005-fiin-vwua 5.4.4 peak theoretical channel throughput an fb-dimm channel transfers read completion data on the northbound data connection. 144 bits of data are transferred for every northbound data frame. this matches the 18-byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 from a single chan nel or a dram burst of four from two lockstepped channels provides a total of 72 bytes of data (64 bytes pl us 8 bytes ecc). the fb- dimm frame rate matches the dram command clock because of the fixed 6:1 ra tio of the fb-dimm channel clock to the dram command clock. therefore, the northbound data connection will exhibit the same peak theoretical throughput as a single dram channel. for example, when using ddr2 533 drams, the peak theoretical bandwidth of the northbound data connection is 4.267 gb/sec. write data is transferred on the southbound command and data connection, via command+wdata frames. 72 bits of data are transferred for every command+wdata frame. two command+wdata frames match the 18-byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ecc). when the frame rate matches the dram command clock, the southbound command and data connection will exhibit one half the peak theoretical throughput of a single dram channel. for example, when using ddr2 533 drams, the peak theoretical bandwidth of the southbound command and data connection is 2.133 gb/sec. the total peak theoretical throughput for a single fb-dimm channel is defined as the sum of the peak theoretical throughput of the northbound data connection and the southbound command and data connection. when the frame rate matches the dram command clock, this is equal to 1.5 times the peak theoretical throughput of a single dram channel. for example, when using ddr2 533 drams, the peak theoretical throughput of a single ddr2-533 channel would be 4.267 gb/sec, while the peak theoretical throughput of the entire fb-dimm pc4200f channel would be 6.4gb/sec. 5.5 hot-add the fb-dimm channel does not provide a mechanism to automatically detect and report the addition of a new dimm south of the currentl y active last dimm. it is assumed the system will be notified through some means of the addition of one or more new dimms so that specific commands ca n be sent to the host controller to initialize th e newly added dimm(s) and perform a hot-add reset to bring them into the channel timing domain. it should be noted that the power to the dimm socket must be removed before a ?hot-add? dimm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 5.6 hot-remove in order to accomplish removal of dimms the host must perform a fast reset sequence targeted at the last dimm that will be re tained on the channel. the fast reset re-establish the appropriate last dimm so that the southbound tx outputs of the last active dimm and the southbound and northbound outputs of the dimms beyond the last active dimm are disabled. once the appropriate outputs are disabled the system can coordinate the procedure to remove power in preparation for physical removal of the dimm if needed. it should be noted that the power to the dimm socket must be removed before a ?hot-add? dimm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 5.7 hot-replace hot replace of dimm is accomplished through co mbining the hot-remove and hot-add process.
data sheet 23 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram electrical characteristics 6 electrical characteristics 6.1 operating conditions table 9 absolute maximum ratings symbol parameter values unit note min. max. v in , v out voltage on any pin relative to v ss ?0.3 1.75 v 1) v cc voltage on v cc pin relative to v ss ?0,3 1.75 v 1) 1) stresses greater than those listed under ?absolute maximum ratings? may ca use permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. v dd voltage on v dd pin relative to v ss ?0.5 2.3 v 1) v tt voltage on v tt pin relative to v ss ?0.5 2.3 v 1) t stg storage temperature ?55 +100 c 1) table 10 operating temperature range symbol parameter values unit note min. max. t case dram component case temperature range 0 +95 c 1)2)3)4) 1) stresses greater than those listed un der ?absolute maximum ratings? may caus e permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) within the dram component case temperature range all dram specific ation will be supported. 3) self-refresh period is hard-coded in the drams and therefore it is imperative t hat the system ensures the dram is below 85c case temperature before in itiating self-refresh operation. 4) above 85c dram case temperature the auto-refresh command interval has to be reduced to trefi = 3.9 s. t case amb component case temperature range 0 +110 c 1) table 11 supply voltage levels and dc operating conditions parameter symbol limit values unit notes min. nom. max. amb supply voltage v cc 1.455 1.5 1.575 v ? dram supply voltage v dd 1.7 1.8 1.9 v ? termination voltage v tt 0.48 v dd 0.50 v dd 0.52 v dd v? eeprom supply voltage v ddspd 3.0 3.3 3.6 v ? dc input logic high(spd) v ih(dc) 2.1 ? v ddspd v 1) dc input logic low(spd) v il(dc) ?? 0.8v 1) dc input logic high(reset) v ih(dc) 1.0??v 2) dc input logi c low(reset) v il(dc) ?? +0.5v 1)
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram electrical characteristics data sheet 24 rev. 1.10, 2005-11 02182005-fiin-vwua leakage current (reset) i l ?90 ? +90 ? 2) leakage current (link) i l ?5 ? +5 ? 3) 1) applies for smb and spd bus signals 2) applies for amb cmos signal reset 3) for all other amb related dc parameters, please refer to the high speed differential link interface specifications table 12 timing parameters parameter symbol min. typ. max. units notes ei assertion pass-thru timing t ei propagate t ? ? 4 clks ? ei deassertion pass-thru timing t eid ?? bitlockclks2 ei assertion duration t ei 100 ? ? clks 1)2) 1) defined in fb-dimm architecture and protocol spec 2) clocks defined as core clocks = 2x sck input fbd cmd to ddr clk out th at latches cmd ? ? 8.1 ? ns 3) 3) @ ddr2-667 - measured from beginning of frame at southbound input to ddr clock output that latches the first command of a frame to the drams fbd cmd to ddr write ? ? tbd ? ns ddr read to fbd (last dimm) ? ? 5.0 ? ns 4) 4) @ ddr2-667 - measured from latest dqs input to amb to st art of matching data frame at northbound fb-dimm outputs resample pass-thru time ? ? 1.075 ? ns resynchpass-thru time ? ? 2.075 ? ns bit lock interval t bitlock ? ? 119 frames 1) frame lock interval t framelock ? ? 154 frames 1) table 13 environmental parameters parameter symbol rating units notes operating temperature t opr see note 1) 1) the designer must meet the case temperature s pecifications for individual module components. operating humidity (relative) h opr 10 to 90 % 2) 2) stresses greater than those listed may cause permanent dam age to the device. this is a stress rating only and the device funcional operation at or abov e the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. storage temperature t stg -50 to +100 c 2) storage humidity (without condensation) h stg 5 to 95 % 2) barometric pressure (operating) p bar 3050 m 2) barometric pressure (storage) p bar 14240 m 2) table 11 supply voltage levels and dc operating conditions parameter symbol limit values unit notes min. nom. max.
data sheet 25 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface 7 high-speed differential po int-to-point link interface the following specificatio ns define the high-speed differential point- to-point signaling link for fb- dimmd, operating at the amb supply voltage of 1.5 v that is provided at the dimm connector. the link consists of a transmitter and a receiver and the interconnect in between them. the transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit- stream. this fb-dimm link is being specified to operate from 3.2 to 4.8 gb/s. the specifications are defined for three distinct bit-rates of operation: 3.2 gb/s (pc2-4200f), 4.0 gb/s (pc2- 5300f) and 4.8 gb/s (pc2-6400f). the link utilizes a derived clock approach and transmitter de-emphasis to compensate for channel loss characteristics. 7.1 differential signaling a differential signal is defi ned by taking the voltage difference between two conductors. in this specification, a differential si gnal or differential pair is comprised of a voltage on a positive conductor, vd+, and a negative conductor, vd -. the differential voltage (vdiff) is defined as the difference of the positive conductor voltage and the negative conductor voltage (vdiff = vd+ - vd-). the common mode voltage (vcm) is defined as the average or mean voltage present on the same differential pair (vcm = [vd++ vd-]/2). this documents elec trical specifications often refer to peak-to-peak measurements or peak measurements, which are defined by the following 5 equations: 1. v diffp-p = (2*max|vd+ - vd-|) (this applies to a symmetric differential swing) 2. v diffp-p = (max|vd+ - vd-| {vd+ > vd-} + max|vd+ - vd-| {vd+ < vd-}) (this applies to an asymmetric differential swing.) 3. v diffp = (max|vd+ - vd-|) (this applies to a symmetric differential swing) 4. v diffp = (max|vd+ - vd-| {vd+ > vd-}) or (max|vd+ - vd-| {vd+ < vd-}) which ever is greater (this applies to an asymmetric differential swing.) 5. v cmp = (max|vd+ + vd-|/2) note: the maximum value is calculated on a per unit interval evaluation. the maximum function as described is implicit for all peak-to-peak and peak equations throughout the rest of this chapter, and thus a max function will not appear in any following representations of these equat ions. in this section, dc is defined as all frequency components below fdc = 30 khz. ac is defined as all frequency components at or above fdc = 30 khz. these definitions pertain to all voltage and current specifications. an example waveform is shown in figure 1-2. in this waveform the differential peak-peak signal is approximately 0.6 v, the differential peak signal is approximately 0.3 v and the common mode is approximately 0.25 v. figure 7 sample differental signal fb-dimmunit interval (ui) - 0 % 4 4ime in ns 6 o l t $ $
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface data sheet 26 rev. 1.10, 2005-11 02182005-fiin-vwua average time interval between voltage transitions of a signal. this is the same as the period of the fb-dimm link bit-rate clock. given a <...1010...> between voltage transitions, over a time interval long enough to make all intentional frequency modulation of the source clock negligible. the ui will be di fferent depend ing on the data rate of operation. ui=312.5ps (pc2-4200f), ui=250ps (pc2-5300f), ui=208ps (pc2-6400f). 7.1.1 transition density in transmitted signals the fb-dimm link doesn?t prescribe encoding. however the link bit stream needs to maintain a minimum transition density. the transition density is defined as the number of trans itions that occurs either from 0 to 1 or from 1 to 0 within any bit stream of a prescribed length. the minimum prescribed transition- density_min is: 6 transitions per 512 bits: fb-dimm at 3.2 gb/s, 4.0 gb/s and 4.8 gb/s. the prescribed minimum is required to enable phase tracking of the received data by the receiver while at the same time minimize the overhead requirements. 7.1.2 jitter and bit error rate jitter is defined as the deviation in the edges of a sequence of data bits from their ideal timing positions. this deviation can be in phase, period or duty cycle. jitter is further categori zed into random jitter and deterministic jitter. the tota l jitter is the convolution of the probability density for all the independent jitter sources. the random jitter magnitude can be approximated as gaussian and can be used to estimate the bit error rate (ber) of the link. in this document the allocation to random jitter and deterministic jitter has no t been separately specified. the total jitter must support a maximum ber of 10 -16. the methods for measuring ber compliance are still being evaluated. 7.1.3 de-emphasis de-emphasis is the engineering term used to describe the technique of utilizing a voltage swing reduction of non-transition bits. figure 1-3 shows an example of a de-emphasized differential signal. de-emphasis is different from pre-emphasis in that non-transition bits are reduced in voltage as opposed to an increase in voltage swing for transition bi ts with pre-emphasis. de- emphasis is included to minimize inter-symbol interference (isi) due to the difference in loss across the frequency band where the main energy of the transmitted bit patterns is located. de-emphasis must be implemented when multiple bits of the same polarity are output in succession. subsequent bits are driven at a differential voltage level below the first bit and individual bits are always driven at the full voltage level, for normal operation. figure 8 de-emphasis 7.1.4 electrical idle (ei) the condition when both conductors of a differential pair are at 0 volt (grounded) level. electrical idle is primarily used in power saving and inactive states (i.e. disable). - 0 % 4 $ $
data sheet 27 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface 7.1.5 reference clock the reference clock networ k consists of the clock generator and the clock buffer that drives the pll of any front-end transmitter or receiver. the same reference clock shall be tr ansmitted to the front-end of the chips at both ends of the link. the reference clock signal meets the high-speed current steering logic (hcsl) specification. 7.2 high speed serial link reference clocks (sck, sck) to reduce jitter and allow fo r future silicon fabrication process changes, hcsl (high-speed current steering logic) clocks are used. the nominal single-ended swing for each clock is 0 to 0.7 v. figure 9 differental reference clock waveform the reference clock frequency is 1/24 of the link data rate, e.g. 166.67 mhz for a da ta rate of 4.0gb/s. the reference clock pair is routed point-to-point to each dimm on the system board. the fb-dimm channel utilizes mesochronous cl ocking, i.e. the phase relationship between tx reference clock and rx reference clock is unspecified. however, in order to limit the jitter difference betw een tx and rx there is an upper limit for the phase difference between data and reference clock at the rx, called the transport delay, t1). 7.3 spread spectrum clocking (ssc) spread spectrum clock (ssc) with up to -0.5% down spread in frequency shall be supported. the frequency of the clock and therefore bit rate can be modulated from 0% to -0.5% of the nom inal data rate/frequency, at a modulation rate in the range between 30 khz and 33 khz. the modulation profile of ssc shall be able to provide optimal or close to optimal emi reduction. typical profiles include tria ngular or hershey profile. 7.4 reference clock input specifications - 0 4 4 4 p e r i o d 3 # + 3 # + table 14 reference clock input specifications parameter symbol values unit notes min. max. reference clock frequency f sck 133.33 200.00 mhz 1)2) rise time, fall time t sck-rise t sck-fall 175 700 psec 3) voltage high v sck-high 660 850 mv voltage low v sck-low -150 mv absolute crossing point v cross-abs 250 550 mv 4) relative crossing point v cross-rel calculated calculated 5)4) % mismatch between rise and fall times t sck-rise-fall-match -10% duty cycle of referance clock t sck-dutycycle 40 60 % clock leakage current i i_ck -10 10 ua 6)7) clock input capacitance c i_ck 0.5 2 pf 7)
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface data sheet 28 rev. 1.10, 2005-11 02182005-fiin-vwua 7.5 differential transmit ter output specifications this specification defines a differential current mode driver with a three different tx voltage swing modes (large, regular and small). the ambs supports all three voltage swing modes. the specification defines several de-emphasis settings for each voltage swing. each setting is defined as a separ ate differential eye diagram that must be met for the tran smitter. figure 3-4 defines the eye heights for the large, regular and small voltage swing. the no de-emphasis voltages are for a transition bit while the other voltages are for a de-emphasized bit. all eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. all eyes must meet the minimum timing requirement of t tx-total- min (specified later). the eye diagrams must be valid for at least n min-ui-tx consecutive uis (specified in table 3- 3). an appropriate average transmitter ui must be used as the interval for measuring the eye diagram. the eye diagram is created using all edges of the n min-ui-tx consecutive uis. the eye di agrams shall be measured by observing a continuous tb d pattern at the pin of the device for the non de-e mphasized eye and by observing a continuous tbd pattern at the pin of the device for the deemphasized eye. the transmitter output eye is referenced to v ss and all transmitter terminations must be referenced to v ss . clock input capacitance delta c i_ck(d) -0.25 0.25 pf 8) transport delay t1 5 ns 9)10) phase jitter samp le size nsample 10 16 periods 11) reference clock jitter, filtered t ref-jitter 40 ps 12)13) reference clock de terministic jitter t ref-dj tbd ps 1) 133mhz for pc2-4200, 166mhz for pc2-5300 and 200mhz for pc2-6400. 2) measured with ssc disabled. 3) measured differentially through t he range of 0.175v to 0.525v. 4) the crossing point must meet the absolute and re lative crossing point specification simultaneously. 5) v cross_rel_(min) and v cross_rel_(max) are derived using the following calculation: min = 0.5 (v havg - 0.710) + 0.250; and max = 0.5 (v havg - 0.710) + 0.550, where v havg is the average of v sck-highm 6) measured with a single-ended input voltage of 1v. 7) applies to reference clocks sck and sck . 8) differance between sck and sck input 9) t1 = |tdatapath - tclockpath| (excluding pll loop delays). th is parameter is not a direct clock output parameter but it indirectly determines the clock output parameter tref-jitter. 10) the net transport delay is the difference in time of flight between associated data and clock paths. the data path is define d from the reference clock source, through the tx, to data arri val at the data sampling point in the rx. the clock path is defined from the reference clock source to clock arrival at the same sampling point. see figure 3-3. the path delays are caused by copper trace routes, on-chip rout ing, on-chip buffering, etc. they include the time-of-fl ight of interpolators or other clock adjustment mechanisms. they do *not* include the phase delays caused by finite pll loop bandwidth because these delays are modeled by th e pll transfer functions. 11) direct measurement of phase jitter record s over 1016 periods is impractical. it is expected that the ji tter will be measured over a smaller, yet statistically significan t, sample size and the total jitter at 1016 samples extrapolated from an estimate o f the sigma of the rando m jitter components. 12) measured with ssc enabled on reference clock generator. 13) as measured after the phase jitter filter. this number is se parate from the receiver jitter budget that is defined by the tr x- total-min parameters. table 14 reference clock input specifications parameter symbol values unit notes min. max.
data sheet 29 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface figure 10 differential requirement minimum transmitter output eye specifications figure 11 illustrates the transmitter timing specifications figure 12 illustrates the de-emphasized string of patterns at the output of a transmitter table 15 differential transmitter output specifications parameter symbol values unit comments min. max. differential peak-to-peak output voltage for large voltage swing v tx-diffp-p_l 900 1300 mv see equation (1) measured as note 1) differential peak-to-peak output voltage for regular voltage swing v tx-diffp-p_r 800 mv see equation (1) measured as note 1) - 0 % 4 4 4 8 4 o t a l m i n 6 4 8 $ ) & & m 6 $ $ # r o s s i n g 0 o i n t 6 4 8 % q m i n , t 6 4 8 % q $ ) & & p p m i n 6 4 8 % q m a x , t ; $ % e m p h a s i z e d " i t s = 6 4 8 $ ) & & m 6 $ $ # r o s s i n g 0 o i n t 6 4 8 $ ) & & p p m i n 6 4 8 $ ) & & p p 6 4 8 $) & & p p m a x - 0 % 4 4 x 4 o t a l m i n 0 u l s e m i n 3 p e c - 0 % 4 4 x m i n 6 d i f f p p . o $ e e m p h a s i s 4 x m i n 6 d i f f p p $ e e m p h a s i s $ $
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface data sheet 30 rev. 1.10, 2005-11 02182005-fiin-vwua differential peak-to-peak output voltage for small voltage swing v tx-diffp-p_s 520 mv see equation (1) measured as note 1) dc common code output voltage for large voltage swing v tx-cm_l 375 mv see equation (2) measured as note 1) dc common code output voltage for small voltage swing v tx-cm_s 135 280 mv see equation (2) measured as note 1) see also note 2) de-emphasized differential output voltage ratio for -3.5 db de-emphasis v tx-de-3.5-ratio -3.0 -4.0 db 1)3)4) de-emphasized differential output voltage ratio for -6.0 db de-emphasis v tx-de-6.0-ratio -5.0 -7.0 db 1)2)3) ac peak-to-peak common mode output voltage for large swing v tx-cm-acp-p-l 90 mv see equation (7) measured as note 1) see also note 5) ac peak-to-peak common mode output voltage for regular swing v tx-cm-acp-p-r 80 mv see equation (7) measured as note 1) see also note 5) ac peak-to-peak common mode output voltage for small swing v tx-cm-acp-p-s 70 mv see equation (7) measured as note 1) see also note 5) maximum single-ended voltage in ei condition dc + ac v tx-idle-se 50 mv 6) maximum single-ended voltage in ei condition dc + ac v tx-idle-se-dc 20 mv 6) maximum peak-to-peak differential voltage in ei condition v tx-idle-diffp-p 40 mv single-ended voltage (w.r.t. vss) on d+/d- v tx-se -75 750 mv 1)7) mimimum tx eye width, 3.2 and 4.0gb/s t tx-eye-min 0.7 ui 1)8) mimimum tx eye width 4.8gb/s t tx-eye-min4.8 tbd ui 1)8) maximum tx deterministic jitter,3.2 and 4.8 gb/s t tx-dj-dd 0.2 ui 1)8)9) maximum tx deterministic jitter, 4.8 gb/s t tx-dj-dd-4.8 tbd ui 1)8)9) instantaneous puls width t tx -pulse 0.85 ui 10) differential tx out out rise/fall time t tx-rise t tx-fall 30 90 ps given by 20 % - 80 % voltage levels. measured as note 1) mismatch between rise and fall times t tx-rf-mismatch 20 ps differential re turn loss rl tx-diff 8 db measured over 0.1 ghz to 2.4 ghz. see also note 11) common mode return loss rl tx-cm 6 db measured over 0.1 ghz to 2.4 ghz. see also note 11) table 15 differential transmitter output specifications (cont?d) parameter symbol values unit comments min. max.
data sheet 31 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface (1) (2) (3) (4) transmitter termination impender r tx 41 55 12) d+/d- tx impedance difference r tx-match-dc 4% see equation (4) bounda are applied separately to high and low output voltages states lane-to lane skew at tx l tx-skew 1 100+ 3ui ps 13)15) lane-to lane skew at tx l tx-skew 2 100+ 2ui ps 14)15) maximum tx drift (resync mode) t tx-drift-resync 240 ps 16) maximum tx drift (resample mode only) t tx-drift-resample 120 ps 16) ber bir error ratio 10 -12 17) 1) specified at the package pins into a timing and voltage comp liance test load as shown in figure 4-2 and in steps outlined in 4.1.2.1. common-mode measurements to be performed using a 101010 pattern. 2) the transmitter designer should not artifically elevate the common mode in order to meet this specification. 3) this is the ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. 4) de-emphasis shall be disabled in the calibration state. 5) includes all sources of ac common mode noise 6) single-ended voltages below that value t hat are simultaneously detected on d+ and d- are interpreted as the electrical idle condition. 7) the maximum value is specified to be at least (v tx-diffp-pl/4 ) + v tx-cml + (v tx-cm-acp-p/2 ). 8) this number does not include the effects of ssc or reference clock jitter. 9) defined as the expected maximum jitter for the given probability as measured in the system (tj), les the unbounded jitter. 10) puls width measure at 0v differential. 11) one of the components that co ntribute to the deteriora tion of the return loss is the esd structure wich needs to be carefull y designed 12) the termination small signal resistance; tolerance across vo ltages from 100 mv to 400 mv shall not exceed +/- 5 w with regard to the average of the values meas ured at 100 mv and 400 mv for that pin. 13) lane to lane skew at the transmitter pins for an end component. 14) lane to lane skew at the transmitter pins for an intermediate component (assuming zero lane to lane skew at the receiver pins of the incoming port). 15) this is a static skew. an fb-dimm component is not allowed to change its lane to lane phase relationship after initializatio n. 16) measured from the reference clock edge to the center of th e output eye. this specification must be met across specified voltage and temperature ranges for a single component. drift ra te change is significantly belo w the tracking capability of the reciver. 17) ber per differential lane. table 15 differential transmitter output specifications (cont?d) parameter symbol values unit comments min. max. v tx diffp ? p ? 2v tx d+ ? v tx d ? ? = v tx cm ? dc avg () of v tx d+ ? v tx d- ? + 2 ? () = v tx cm ? ac ? max v tx d+ ? v tx d- ? + () 2 ? () min v tx d+ ? v tx d- ? + () 2 ? ( ) ? = r tx match ? dc ? 2 r tx-d+ r tx-d- ? r tx-d+ r tx-d- + ------------------------------------------- =
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface data sheet 32 rev. 1.10, 2005-11 02182005-fiin-vwua 7.6 differential receiver input specifications the receiver definition starts from the input pin of t he receiver end package and therefore includes the package and the receiver end chip. 7.6.1 receiver i nput compliance eye specification following the specification of the transmitter, the receiver is specified in te rms of the minimum input eye that must be maintained at the input to the receiver, and under which the receiver must function at the specified data rates. the receiver ey e is referenc ed to vss and all input terminations at receiver must be referenced to vss. this input eye must be maintained for at least nmin-ui-rx consecutive ui s. an appropriate average transmitter ui must be used as the interval for measuring the eye diagram. the eye diagram is created using all edges of the nmin-ui-tx consecutive uis. the eye diagrams shall be measured by observing a continuous tbd pattern at the pin of the device. figure 13 required receiver input eye (different ial) showing minimum voltage and timing spec. table 16 differential recei ver input specifications parameter symbol values unit comments min. max. differential peak-to-peak input voltage v rx-diffp-p 170 tbd mv see equation (5) measured as note 1) maximum single-ended voltage for ei condition v rx-idle_se 75 mv 2)3) maximum single-ended voltage for ei condition(dc only) v rx-idle_se_dc 50 mv 2)3) maximum peak-to-peak differental voltage for ei condition v rx-idle-diffp-p 65 mv 3) single ended voltage (w.r.t. vss) on d+/d- v rx-se -300 900 mv 4) single-pulse peak differential input voltage v rx-diff-pulse 85 mv 4)5) amplitude ratio between adjacent symbols v rx-diff-adj-ratio tbd 4)6) maximum rx inherent timing error, 3.2 and 4.0 gb/s t rx-tj-max 0.4 ui 4)7)8) maximum rx inherent timing error, 4.8gb/s t rx-tj-max4.8 tbd ui 4)7)8) maximum rx inherent deterministic timing error, 3.2 and 4.0 gb/s v rx-dj-dd 0.3 ui 4)7)8)9) - 0 % 4 4 2 8 4 o t a l m i n 6 2 8 $ ) & & m 6 $ $ # r o s s i n g 0 o i n t 6 2 8 $) & & p p m i n 6 28 $ ) & & m 6 $ $ # r o s s i n g 0 o i n t
data sheet 33 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface maximum rx inherent deterministic timing error, 4.8 gb/s v rx-dj-dd-4.8 tbd ui 4)7)8)9) single-puls width at zero-voltage crossing t rx-pw-zc 0.55 ui 4)5) single-puls width at minimum-level crossing t rx-pw-ml 0.2 ui 4)5) differential rx inpu t rise/fall time t rx-rise, t rx- fall, 50 ps given by 20 % - 80 % voltage levels. common mode of the input voltage v rx-cm 120 400 mv see equation (6) measure as note 1) , see also note 10) ac peak-to-peak common mode of input voltage v rx-cm-acp-p 270 mv see equation (7) note 1) ratio of v rx-cm-acp-p to minimum v rx-diffp- p v rx-cm-eh-ratop 45 % 11) differential re turn loss rl rx-diff 9 db measured over 0.1 ghz to 2.4 ghz. see also note 12) common mode return loss r rx-cm 6 db measured over 0.1 ghz to 2.4 ghz. see also note 12) rx termination impendance r rx 41 55 ? 13) d+/d- rx impendance difference r rx-match-dc 4 % see equation (8) lane-to-lane pcb skew at rx l rx-pcb-skew 6 ui lane to lane skew at the receiver that must be tolerated. see also note 14) minimum rx drift tolerance t rx-drift 400 ps 15) minimum data tracking 3 db bandwidth f trk 0.2 mhz 16) electrical idle entry datect time t ei-entry- detect 60 ns 17) electrical idle exit datect time t ei-entry- detect 30 ns bit error ratio ber 10 -12 18) 1) specified at the package pins into a timing and voltage complia nt test setup. note that sign al levels at the pad will be lowe r than at the pin. 2) single-ended voltages below that value that are simultaneously detected on d+ and d- are interpreted as the electrical idle condition. worst-case marg ins are determined for the case with transmitter using small voltage swing. 3) multiple lanes need to detect the ei condition before the device can act upon the ei detection. 4) specified at the package pins into a timing and voltage compliance test setup. 5) see figure 3-8 and figure 3-9. the single-pulse mask provides sufficient symbol energy for reliable rx reception. each symbol must comply with both the singl e-pulse mask and the cumulative eyemask. 6) see figure 3-10. the relative amplitude ratio limit between adjacent symbols prevents excessi ve intersymbol interference in the rx. each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. table 16 differential recei ver input specifications parameter symbol values unit comments min. max.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram high-speed differential point-to-point link interface data sheet 34 rev. 1.10, 2005-11 02182005-fiin-vwua (5) (6) (7) (8) 7) this number does not include the effects of ssc or reference clock jitter. 8) this number includes setup and hold of the rx sampling flop. 9) defined as the dual-dirac deterministic timing error. 10) allows for 15 mv dc offset between transmit and receive devices. 11) the received differential signal must satisfy both this ratio as well as the absolute maximum ac peaktopeak common mode specification. for example, if v rx-diffp-p is 200 mv, the maximum ac peak-to peak common mode is the lesser of (200 mv * 0.45 = 90 mv) and v rx-cm-ac-p-p . 12) one of the components t hat contribute to the deterioration of the return loss is the esd structure which needs to be careful ly designed. 13) the termination small signal resistance; tolerance across vo ltages from 100 mv to 400 mv shall not exceed +/- 5 w with regard to the average of the values measur ed at 100 mv and at 400 mv for that pin. 14) this number represents the lane-to-lane skew between tx and rx pins and does not include the transmitter output skew from the component driving the signal to the receiver. this is one component of the end-to-end channel skew in the amb specification. 15) measured from the reference clock edge to the center of th e input eye. this specificatio n must be met across specified voltage and temperature ranges for a single component. drift rate of change is signif icantly below the tracking capability of the receiver. 16) this bandwidth number assumes the specified minimum data tran sition density. maximum jitter at 0.2 mhz is 0.05 ui, see section 4 for full jitter tolerance mask. 17) the specified time includes the time r equired to forward the ei entry condition. 18) ber per differential lane. refer to section 4 for a complete definition of bit error ratio. v rx diffp ? p ? 2v rx-d+ v rx-d- ? = v rx cm ? dc avg () of v rx d+ ? v rx d- ? + = () 2 ? v rx cm ? ac ? max v rx d+ ? v rx d- ? + () 2 ? () min v rx d+ ? v rx d- ? + () 2 ? () = r rx match ? dc ? 2 r rx-d+ r rx-d- ? r rx-d+ r rx-d- + -------------------------------------------- - =
data sheet 35 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel initialization 8 channel initialization the fb-dimm channel initialization process generally follows the top to bottom sequence of state transitions shown in the high level amb initialization flow diagram in figure 3-4. the host must sequence the amb devices through the disable, calibrate, (back to disable), training, testing, and polling states in order to transition the ambs into the active channel l0 state. the value in parenthesis in each state bubble indicates the condition/activity of th e links during these states. figure 14 flow chart amb initialization 8.1 reset signal the reset signal acts as a hardware reset and immediately puts the amb into a known state. the amb initialization fsm is put into the disable state and the nb tx outputs are put into electrical idle regardless of the state of the nb rx inputs . all ?sticky? bits are set to their default values. the cke signals to the dram devices are driven inactive to turn off the dram output drivers. dram specific me chanisms in the amb may generate additional signal transitions to the dram devices to make sure that they do not hang in an unknown state. the amb specification for each dram technology defines any dram specific mechanisms. if the drams were in self re fresh prior to reset being asserted, they will remain in self refres h through the hardware reset. the host must wait until the power and the reference clock to the ambs have been stable for greater than or equal to 1ms before transitioning the channel out of the disabl e state. the relationship between supply voltage, reference clock and the reset signal is define d in the amb buffer specification 8.1.1 inband control ?signals? there are no dedicated control signals implemented on an fb-dimm channel. two different channel characteristics are exploited to deliver inband control information on the fb-dimm channel wires when no - 0 & 4 $ i s a b l e 0 o w e r u p # a l i b r a t e | s 4 r a i n i n g 4 3 / 4 e s t i n g 4 3 0 o l l i n g 4 3 # o n f i g 4 3 , / f r a m e s 2 e c a l i b r a t e . / 0 s , / s %
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel initialization data sheet 36 rev. 1.10, 2005-11 02182005-fiin-vwua clock timing has been established between the host and the ambs: electrical idle (ei): during normal channel operation the tx outputs are enabled and a differential voltage is present on each bit lane. in electrical idle the tx outputs source insignificant current and the termination resistors at the receiver pull both signals of the differential pair to ground. the rx inputs can detect if both differential inputs are near ground to receive inband control information. clock training violation: during normal channel operation the southbound bit lanes cont ain a minimum number of transitions every tclktrain frames to keep the clock tracking circuits on each bit lane locked to the data stream. it is the absence of these periodic bit lane transitions that is used by the host to communicate control information.. 8.2 channel initialization sequence the host controller sequen ces the fb-dimm channel through the initialization sequence. the amb devices on each dimm monitor in-band signals from the host and use events and patterns on these signals to transition from one state to another. if the channel fails to initialize properly the host may transition the channel back to the disable state and try again a number of times before reporting a failure to the system. it is undesirable to continuously drive high frequency signals into un-terminated transmission lines because of the emi that is generated and the power that is wasted. to avoid this the host must return to the disable state if the channel does not properly initialize. 8.2.1 firmware transition control the channel initialization and configuration sequence may be controlled by a hardware state machine or directed by firmware. to provide a flexible mechanism for dealing with a variety of fb-dimm channel failure conditions it is recommended that the channel initialization and configuration process be controlled by firmware. it is recommended that implementation specific control registers be included in the host to allow firmware to step through the initialization steps and perform the following functions: ? put the sb tx outputs into electrical idle. ? drive sb tx outputs to all ones. ? detect if the nb port is receiving electrical idle. ? drive ts0 patterns with an arbitrary amb_id value. ? receive ts0 patterns and read the returned amb_id value ? drive ts1 patterns with an arbitrary amb_id value and wi th a sequence of electric al stress test patterns on each bit lane. registers to hold an arbitrary 24 bits of test parameter values are recommended. ? receive ts1 electrical stress test patterns and check the patterns. ? test the nb bit lanes and report nb test results. ? drive ts2 patterns. ? receive ts2 patterns and determine the round trip channel delay. ? drive ts3 patterns with channel configuration values. ? receive ts3 patterns and check the returned values. ? set the last_amb_id value. ? set the hot_add_amb_id value ? set the fast_reset_flag value. ? set the recalibrate_duration value. ? set the l0s_duration value. ? transition the channel to the l0 st ate and send the first sync command. 8.2.2 amb internal state variables a number of internal flags and timers are referenced in the following sections. these flags and timers are implementation specific and included in the state tables to describe internal amb state that may or may not be visible in defined amb registers. these flags and timers include: ? last_amb_flag - set in the last amb to enable unique properties of the amb in this position.
data sheet 37 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel initialization ? first_sync_received_flag - set to disable furthe r initialization of the idle/alert frame lfsr. ? idle/alert frame lfsr - a counter in each amb used to generate idle and alert frames on the nb channel. ? alert_flag - a flag that indicated that this amb detect ed an error and is or was generating nb alert frames. ? recalibrate_timer - a timer that keeps track of ho w long the amb has been in the recalibrate state. ? l0s_timer - a timer that keeps track of how long the amb has been in the l0s state. 8.2.3 disable state the channel is forced into the disable state during hardware reset. the host may put the channel into the disable state at any time and from any other state other than l0s by putting the three least significant tx outputs into electrical idle . the host must not put the channel into the disable state from the l0 state until any dram write operations have had time to complete. channel initialization always starts in the disable state. 8.2.4 training state the host drives a repetitive series of ts0 patterns to transition the ambs from the disable state to the training state and to perform initial link training. the host may detect that the la st amb has acquired frame lock when ts0 patterns are received on the required number of inputs. bit patterns in ts0 are used to perform bit lock and frame lock. the pattern is mostly filled with an alter nating 1010 pattern to align the clock trackers with the incoming data stream. the sequence generally has logic zeroes in the even bit positions and logic ones in the odd bit positions. the beginning of the sequence is identified by the header pattern shown in the table below and is used to establish the alignment of the serial data onto frame boundaries. 8.2.5 testing state the host drives a ts1 pattern to transition the ambs from the training state to the testing state and may send an arbitrary number of ts1 patterns to test the channel. 8.2.6 polling state the host drives a ts2 pattern to transition the ambs from the testing state to the polling state. the host sends a continuous stream of ts2 patterns to the last amb to determine the round trip latency of the channel. the host may subsequently and optionally send a ts2 pattern to each in termediate amb to test if it has aligned its northbound merge data timing to the timing of the last amb and can properly merge its data into the northbound data stream. 8.2.7 config state the ts3 training sequence is used to communicate the cha nnel configuration to the ambs in the config state. on exit transitions to l0 state if 4 co nsecutive nop frames are received.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol data sheet 38 rev. 1.10, 2005-11 02182005-fiin-vwua 9 channel protocol the host performs all of the scheduling of the southbound and northbound data paths. the fb dimms do not initiate any northbound traffic but instead respond to commands provided by the host. this protocol style results in a memory channel that has deterministic behavior (in the absence of error events) and facilitates the use of two or more fb-dimm channels in lock stepped configurations. the host sends commands and data to the dimms in 120-bit southbound frames. similarly the dimms return data to the host in 168-bit northbound frames. 9.1 southbound frames after initialization the ho st communicates with the ambs on the channel using southbound frames of information containing commands and data. there are two modes of operation of the southbound channel, normal and fail-over. in normal mode the southbound link is full width and has a stronger crc code. in fail- over mode the southbound link is reduced in width by one bit and uses a weaker crc code. 9.1.1 normal southbound frames normal southbound frames consist of 12 transfers of data delivered on 10 southbound bit lanes. each frame contains 72-bits of data, 24 -bits of command, 2-bits of command type and is protected by 22-bits of crc information. 9.1.2 fail-over southbound frames fail-over southbound frames consist of 12 transfers of data delivered on 9 southbound bit lanes. the most significant bit lane is not available to carry crc bits in fail-over mode and the crc code size is reduced in this mode. 9.1.3 command frame format the command frame contains up to three independent commands that can be executed in parallel by separate dimms and in some cases by the same dimm. bits in each command specify which dimm should execute the command. 9.1.3.1 command frame with data format specific commands, such as configuration register write commands, may need to deliver data to the amb devices. the command frame is used by these commands to deliver a data payload with information that cannot be encoded in the command itself. 9.1.3.2 command+wdata frame format the command+wdata frame is used to deliver write data to write fifo structures on each dimm for future transfer to the dram devices. the content of the data payload is not examined by the amb. the write data is loaded into the write fifo on the dimm from 3 consecutive command+wdata frames. 9.1.4 southbound commands there are two categories of southbound commands. dram commands and channel commands. 9.1.4.1 dram commands dram commands are generated by the host to access the dram devices behind each amb buffer. the host has access to the dram devices as if the devices were directly connected to the host. the amb decodes the
data sheet 39 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol dram commands and generates the control signals to the dram devices. the command delivery on the dram address and control signals (excluding cke) use 1n command timing. 1n command timing means that the commands are pres ent on the dram pins for a single clock cycle. dram read and write commands always transfer complete bursts of data determined by the burst length field programmed into the dram mrs registers. a burst length of 4 will transfer 36 bytes and a burst length of 8 will transfer 72 bytes to/from each ecc dimm. non-ecc memory dimms support the data mask function. wr ite accesses transfer the data from the write data fifo located inside the amb device on the dimm. a register instructs the amb when to drive the data after the write command. the ddr2 specific off-chip driver (ocd) impedance adjust command also transfers data from the write data fifo to the dram devices. the host is responsible for memory ordering, fb-dimm channel scheduling, and error handling. available dram commands ? activate ?write ? read ? precharge all ? precharge single ? auto refresh ? enter self refresh ? enter power down ? exit self refresh and exit power down 9.1.4.2 channel commands channel commands include the sync command, miscellaneous dram commands, configuration register read and write commands, and miscellaneous maintenance commands. available channel commands ? channel nop ? sync ? soft channel reset ? write config register ? read config register ? dram cke per dimm ? dram cke per rank ? debug 9.1.4.3 cke control commands two versions of the cke control command allows for individual rank control, where up to 4 dimms may be targeted at once, or per dimm control, where all 8 dimms can be accessed from a single command. the cke control commands will af fect the cke pins for the addressed dimm(s) with the same timing as a dram command, based on slot lo cation. multiple cke commands may be included in one frame as long as no more than one of the commands targets any one dimm on the same dram clock. the host controller is responsible for cke timing with respect to the dram protocol, including the explicit self refresh command. the amb will not do any prot ocol checking. the per dimm cke command allows a ll 8 dimms to be targeted by a single command. the per rank cke command allows for individual rank cke control. 9.1.4.4 soft channel reset command the soft channel reset command may be used to attempt to recover from a tr ansient bit failure on the channel. in the case of a minor transient bit error a single or a small group of commands may be corrupted.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol data sheet 40 rev. 1.10, 2005-11 02182005-fiin-vwua the amb will detect the corruption as a crc error and will ignore the co rrupted commands and report the error to the host with alert frames. the host may issue a soft channel reset command to acknowledge the receipt of the alert frames and reset the command state of the ambs. the soft channel reset command must be preceded by at least 1 nop frame and followed by at least 4 nop frames. the amb recognizes the soft channel reset command while ignoring all others and resets its internal command state. the following actions are performed by the amb: ? discontinue alert frame generation and generate idle frames or forward nb traffic in the frame that a status return would be located if the soft channel reset command was a sync command. ? discard all data content in the write fifo ? reset the dimm target wr ite fifo state machine the host may follow the so ft channel reset command (and the 4 nop frames) with a sequence of dram commands to clear the command state of the dram devices. the sequence may look something like this: 1. assert cke to all ranks 2. wait the appropriate number of clocks 3. issue a precharge all command to all ranks if the soft channel reset itself is corrupted the stream of alert frames will continue and the host may perform a fast reset to reinitialize the channel. 9.1.4.5 sync command the fb-dimm channel periodically requires a minimum number of transitions on each bit lane to maintain clock recovery synchronization. the host must periodically send a sync command on the channel to maintain the required transition density. the maximum interval between sync frames is 42 frames, in order to maintain clock recovery synchronization. the host controller must adhere to a minimum interval between sync frames to guarantee that the amb clock recovery circuits will be adjusted. this allows the amb to save power by switching off internal circuits between sync commands. the amb contains a register in which the host controller programs t he minimum interval between syncs which it will send. the host controller may then send syncs at any interval between the programmed interval and 42. for exampl e, if the host controller design can send syncs in the range of 38 to 42 frames apart, the register would be programmed to 38. the best power management for the amb can be achieved by the host controller being as consistent as possible in its sync generation. power management within the amb can have an impact on bandwidth capabilities in some platforms. the amb specification provides information on the programming of this register as well as the default and minimum values. following a reset, the host may ignore the minimum sync interval up until the 4th sync. 9.1.4.6 nop frame the nop frame contains three nop commands and is sent on the southbound link when there are no other commands to send on the channel. the frame is a normal command frame format. 9.1.4.7 command delivery timing dram access latency is minimized by allowing the command to be delivered to the dram immediately after the first 4 transfers of the frame have been received. 9.1.4.8 concurrent command delivery rules commands may be issued in any combination, as long as they do not collide on any dram pin or fb-dimm data slot, and follow a fe w additional rules below. dram command and address pins only one of the following commands may target a particular dimm in the same dram clock due to collisions on the dram co mmand and address pins. multiple commands within this list may be issued if each targets a differ ent dimm, as long as there is no collision on the fb-dimm channel northbound data bus:
data sheet 41 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol activate, write, read, precharge single, precharge all, auto refresh, and enter self refresh. dram cke pins only one of the following commands may target a particular dimm in the same dram clock due to collisions on the cke pins: en ter self refres h, exit self refresh, dram cke per dimm, dram cke per rank, and enter power down. note that dram cke commands may target a single dimm, or 4 or 8 dimms at once. when multiple dimms are targeted by a command, no other command affecting the cke pins may be issued to any of the targeted dimms. dram data and strobe pins commands cannot be issued to a dimm that would cause collisions on the dr am data and strobe pins within a dimm. in addition, all turnaround times for the dram data and strobe pins must be observed. northbound data bus commands cannot be issued on the channel that would cause collisions on th e northboun d data bus. commands that generate data on the northbound data bus are: read, read config reg, and sync. the order of responses must be pr eserved. commands issued following a sync command with sd > 0 must not return data before or on top of the sync status return. other restrictions only one outstanding configuration read or write register transaction is allowed on the channel. a configuration register read begins with the command and ends with the data being returned to the host. a configuration write begins with the command and ends when the read data would have been returned if the command were a read config reg. this is the same point that an alert frame would be generated if there were a crc error on the write config reg command. allowing only one outstanding configuration transaction on the bus allows for proper replay of the write config reg command following an alert frame. a soft channel reset requires no p commands in all other command slots in the previous dram clock, the current dram clock, and the next 4 dram clocks. only one in- band debug event may be sent within a dram clock. the host controller is responsible for state and timing of the cke pins vs. dram commands based on the dram specifications. a dram command and cke command may target the same dimm on the same dram clock provided that the dram specifications are met. 9.1.4.9 command encoding commands are encoded into the 24 bit of command frames. for detailed command bit maps please refer to the amb buffer specification. 9.2 northbound crc modes fb-dimm supports three northbound crc modes to support applications that requi re different levels of error detection. the frames contain two 72-bit or 64-bit data payloads. each data payload is protected by either a 12-bit crc or a 6-bit crc. the three supported northbound crc modes are: 14 bit lanes: 12-bit crc over 72-bit data payload, fail-over to 6-bit crc 13 bit lanes: 6-bit crc over 72-bit data payload, fail-over to ecc coverage only 12 bit lanes: 6-bit crc over 64-bit data payload, no fail-over the selection on the mode of operation is controlled by the host and communicated during the initialization pr ocess. northbound crc is only computed for data fr ames. the idle, alert, and status frame types drive the upper bit lanes with a known data pattern. during fail-over the host simply ignores the missing bit lanes.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol data sheet 42 rev. 1.10, 2005-11 02182005-fiin-vwua 9.2.1 northbound idle frame each idle frame contains a permuting data pattern. the last dimm on the channel sends this permuting data pattern when not sending requested data from the dimm. the content of the frame is designed to intentionally generate crc errors if not in fail-over mode so that the host can easily detect when an expected northbound data frame with good crc is missing. the host does not log the crc errors generated by the idle fram es. host hardware will issue a sync command on the channel immediately following entry into the l0 state to reset the permuting data pattern of the idle and alert frames to their initial value. the first idle frame follows immediately after the status frame returned for the first sync command. the permuting data pattern is generated by a 12-bit linear- feedback shift register (lfsr) with a polynomial of x12 +x7 + x4 + x3 + 1. the lfsr counter cycles through 212-1 states (4095 frames) before the pattern is repeated. each bit of the counter is mapped onto a corresponding northbound bit lane. the lfsr does not generate an all zero data payload. 9.2.2 northbound alert frame ambs report detection of errors on the channel using the northbound alert frame. the northbound alert frame contains the inverse of the idle frame data pattern. the host may use detection of this permuting data pattern to indicate that an error has occurred. an amb on the channel will s end this permuting data pattern after it has detected a crc error in any southbound command frame. the amb will continue to generate northbound alert fr ames until it receives a soft channel reset command or a channel reset. 9.2.3 northbound data frames this section defines the fo rmat of the northbound data frames. each frame contains either two 72-bit data payloads or two 64-bit data payloads. a crc code is computed across each of the 72-bit data payloads and is sent on the 12th, 13th, or 13th & 14th bit lanes if not in fail-over mode. each data payload has its own crc code to minimize the latenc y to deliver the first data payload to the host. 9.2.3.1 14-bit lane northbound data frame this is the highest ras mode of operation for the northbound channel. in this mode a 12-bit crc is delivered during the transfer of each 72-bit data payload. for the mapping of the data from each of the dram devices into the northbound data frame please refer to the amb buffer specification. 9.2.3.2 13-bit lane fail-over northbound data frame when the 14 lane mode has failed over to 13 lanes, the northbound data frame is identical to the 13 bit lane frame below. 9.2.3.3 13-bit lane northbound data frame this is the medium ras mode of operation for the northbound channel. in this mode a 6-bit crc is delivered during the transfer of each 72-bit data payload. for the mapping of the data from each of the dram devices into the northbound data frame please refer to the amb buffer specification. 9.2.3.4 13-bit lane fail-o ver northbound data frame when 13-bit lane mode has failed over and is operating on 12 lanes, each transfer consists of only the 72 bit payload with no crc. the ecc implemented by the host is the only error detection available. note that this frame format is not the same as the 12-bit lane frame format.
data sheet 43 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol 9.2.3.5 12-bit lane northbound data frame (non-ecc mode) this is the lowest ras mode of operation for the northbound channel. in this mode a 6-bit crc is delivered during the transfer of each 64-bit data payload. the data payload does not contain ecc bits and the crc code is the only fo rm of protection. for the mapping of the data from each of the dram devices into the northbound data frame please refer to the amb buffer specification. 9.2.3.6 northbound regi ster data frame the nb register data frame is used to return data in response to a read configuration command. the frame always returns 32-bits of register data. the host must select the appropriate bytes from the four data bytes delivered if fewer than four bytes are needed. 9.2.3.7 northbound status frame the status frame is returned to the host in response to a sync command from the host. the status returned in the status frame corresponds to the status of the amb to commands before the sync command. errors that are generated by commands after the sync command are reported in subsequent status frames. in other words the sync command provides a fence for status reporting. each amb will me rge its status into the northbound bit stream on the appropriate bit lane. the northbound status frame contai ns a group of status bits from each amb. the status bits are protected by an odd parity bit dnsp that covers the status bits from each amb individually. this is necessary because the status from each amb is merged on-the-fly? into the status frame by each amb and a crc that covers all of the status bits could not be calculated within this mechanism. each amb drives all 12 bits delivered in the frame for its assigned bit lane, including the alternating one/zero pattern. the amb in the last dimm position of the daisy chain initiates the northbound status frame and fills the bi t lane corresponding to its dimm position with its status information and fills the remainder of the bit lanes with a zero status code and an invalid zero parity value. this is done so that the host may detect a missing status response if an amb misinterprets the sync comm and. the host is expected (but not required) to detect the status response error and reissue the sync command to request the status again. the crc bit lanes are filled with the same fixed pattern because the crc is no t valid in this frame type. 9.3 dram memory timing the host accesses the dram devices on an fb-dimm dimm as if they were directly connected to the host but with a few differences. first there is generally a longer than usual delay in the return data path between the dram and the host,and second there is a fifo mechanism in the write data path between the host and the dram. the host sends ?ras? and ?cas? style commands directly to the dram devices. the commands on the fb-dimm channel are delivered to the dram devices with a fixed delay. the host controller must deliver commands onto the fb-dimm channel exactly as the host intends the commands to be delivered to the dram devices. this section illustrates the dram timing on the channel. the command delivery on the dram address and control pins use 1n command ti ming. 1n command timing means that the commands are present on the dram pins for a single clock cycle. this allows the commands present on the channel to be forwarded to the dram channel without timing modification. 9.3.1 read timing the command timing of the dram devices on an fb- dimm is identical to the timing of an individual dram device. the ras latency, cas latency, etc. are controlled by the mrs values loaded into the dram devices. figure 4-15 illust rates an example dram read operation. the data returned to the host is delayed for an interval of time determined by the propagation delay characteristics of the channel. for single dimm configurations the timing behaves similar to a registered sdram di mm. as dimms are added to the channel the accumulated delay due to pcb flight time and delay through intermediate amb components increases the delay in the return data path.
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol data sheet 44 rev. 1.10, 2005-11 02182005-fiin-vwua figure 15 basic dram read data transferes on fbd (rd) back-to-back reads from diff erent dimms is illustrated in figure 4-16. unlike ddr2, the data from the separatedimms can be returned without a dead clock between the data bursts. figure 16 back-toback dram raed data transferes on fbd (rd-rd) 9.3.2 write timing the write command timing of a dram device on an fb- dimm is identical to the timing of an individual dram device. the write latency is controlled by the mrs values loaded into the dram devices. figure 4-17 illustrates an example dram write operation. the host transfers the data to be writ ten into a write fifo in the amb preceding the dram write transfer. the write fifo is used to accumulate write data in the amb so that the data can be transferred to the dram devices at full burst rate during the write operation. the host must be aware of the dram write latency value in order to make sure that the write data is available in the write fifo early enough to be delivered to the drams when expected. the amb mu st be aware of the dram write latency value in order to deliver the write data to the drams when expected . note that the write command may be issued before the frame holding the last payload of data. the figure shows the shortest time between the last frame of data is driven on the southbound channel and when the data can be driven onto the dram data pins. the data can be loaded into the fifo earlier than what is shown but will occupy an entry in the fifo until used. the fixed fall through time shown defines the just-in-time arrival of the data to meet delivery to the dram. this just-in-time arrival time allows the controller to deliver a burst of 64 transfers to the dram using the 35 deep fifo in the amb. writes may be followed by a sync command that returns status information to indicate to the host that no errors are associated with the write operation(s). the &"$?3outhbound $)--?cmd $)--?$ata $)--?cmd $)--?$ata &"$?.orthbound !#4 2$ !#4 2$ 4 4 4 4 4 4 4 4 4 4 4 4 4 mptt ./0 ./0 ./0 ./0 )%'b6rxwkerxqg ',00bfpg ',00b'dwd ',00bfpg ',00b'dwd )%'b1ruwkerxqg $&7 $&7 5' 5' $&7 5' $&7 5' 7 7 7 7 7 7 7 7 7 7 7 7 7 psww 123 123 123 123 123 123 123 123
data sheet 45 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram channel protocol figure shows the earliest the sync command can be issued and report completion of the write operations. if there are errors with the write command or the write data the amb will report th e error by sending alert frames. following error detection, the host may issue the soft channel reset command to discard any data in the write fifo. this wo uld empty the write fifo and put the write fifo state machines into a known state. figure 17 basic dram write data transferes on fbd (wr) 9.3.2.1 write data fifo the write data fifo is a data structure that is used to accumulate write data in the amb in preparation for bursting the data to the dram devices. the fifo can be filled at a maximum of half of the dram burst rate but is emptied at the full dram burst data rate. the command+wdata frames contain a data payload of 72-bits that is loaded into the designated write fifo. the command+wdata frames are not required to be contiguous and may be separated by an arbitrary number of intervening frames. the write fifo on each dimm can hold thirty-five (35) 72-bit data payloads. multiple bursts of data can be accumulated in the fifo to amortize the read-write-read dram data bus turnaround penalty over a number of write operations. the dram write command pulls the data from the head of the fifo and delivers it to the dram devices in the clock cycle determined by register settings in the amb. additional data can be loaded into the fifo while data is being delivered to the dram. the depth of the fifo supports a continuous burst of 64 transfers to the dram devices. 9.3.3 simultaneous read a nd write data transfers the fb-dimm channel provides separate data path for read completion data and write request data. because each fb-dimm contains an isolated dram channel behind the amb component, read data from the dram devices on one fb-dimm can be read at the same time that write data is being writ ten to the dram devices on another fb-dimm. 9.3.4 dram bus segment restrictions either one or two ranks of dram devices may be located behind the amb on an fb-dimm. these devices sit on a dram bus segment and must observe the restrictions on the usage of the bus segment. the ddr2 sdram data sheets should be referenced for details of the restrictions. a dead time is required between read operations for ddr2 devices from the two separate ranks to avoid electrical conflict on the dqs and dqs signals. the turnaround times for dead times such as read-to-read, read-to-write, and write-to- read are dimm layout specific and are captured in the spd eeprom on the dimm. these parameters are readable by firmware to direct the appropriate behavior of the host controller. )%'b6rxwkerxqg ',00bfpg ',00b'dwd ',00bfpg ',00b'dwd )%'b1ruwkerxqg $&7 123 :5 123 123 6<1& $&7 :5 6wdwxv 7 7 7 7 7 7 7 7 7 7 7 7 7 psww 123 123 :gdwd :gdwd :gdwd :gdwd :gdwd :gdwd )l[hgidoowkurxjkwlph :gdwd :gdwd
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram reliability, availabi lity and serviceability data sheet 46 rev. 1.10, 2005-11 02182005-fiin-vwua 10 reliability, availab ility and serviceability 10.1 overview the fb-dimm channel specification provides comprehensive ras support in cluding, error detection and frame transmission retry, error logging, error injection, host add/remove of dimms, and the mechanisms for in-operation test and fault recovery using the fast reset capability of the channel. the philosophy for fb-dimm channe l reliability is to provide strong error detection of channel transaction errors, and the ability to re try the transaction s after automatic hardware recovery. both the northbound and southbound links include fail-over mechanisms that can keep the links running after any one wire fails with enough fault detection to maintain reliable operation until repair. the fb-dimm channel protects data from errors using crc codes ge nerated by both the host and the amb. fb-dimm provides error detection and retry mechanisms for commands and data. it further provides an alert frame reporting mechanism whereby the host is made aware of errors found by an amb in the command or (write) data. a status response mechanism is provided to return to the host quick abbreviated status information from all of the ambs simultaneously. an amb will discard any commands or data received with a crc error. for reads, the read data that is returned to the host with correct ecc and/or crc is the positive acknowledgement that all has transpired without error. if the host does not receive a read return when scheduled, or if the read return contains an error, the host may reissue the read command or the entire read sequence, and/or send a sync command to acquire er ror status from the ambs. error free writes are silently accepted by the amb with no response returned to the host. write data or any commands that are received by the amb in error will cause the amb to notify the host through alert frames. alert frames are continuously sent until acknowledged by the host with a soft channel reset command or a channel reset. 10.2 example error flows this section gives an info rmal overview of error handling by walking through example write and read flows. precise details follo w in subsequent sections. 10.2.1 command error flow the amb checks for errors in all commands but cannot discriminate one failed type of command from any other type of command. all command errors are reported to the host and all subsequent commands except soft channel reset are ignored. command errors are reported to the host by a str eam of alert frames in place of normally returned frames. upon receiving an alert response indicating that there was a command error, the host may issue a soft channel reset command or a fast reset to attempt to recover from the error. the amb will close all dram pages and place the dram devices into self-refresh upon detection of the fast reset. following the fast re set the host may reissue all read and write transactions since the previous verified transaction completion and continue normal operation. 10.2.2 write data error flow the amb checks for errors in the write data by computing a 22-bit crc covering the write data frame. when in wire fail-over mode a 10-bit crc is available to check for link transmission errors in the write data. crc errors detected in the write data are reported to the host the same as command errors. 10.2.3 read error flow a read differs from a write primarily in that the amb provides a positive acknowledgement that there were no errors with the read command through the delivery of the read data in the specified northbound data frame. if the amb detects an error in a read command, the amb discards the command and alert frames will be
data sheet 47 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram reliability, availabi lity and serviceability returned. upon receiving a read return, the host verifies that it has received the corr ect amount of data at the scheduled time, and checks the correctness of the data. if any of these are in error the read command may either be retried or the host may attempt to correct the [data] error. section 5.7 describes the algorithm in more detail. 10.3 overview of error protection, detection, correction, and logging fb-dimm uses several different mechanisms for error protection, detection, corr ection, and error logging. error handling elements are made up of the following: southbound commands and data b a) the host computes check bits for commands -14-bit crc on a per command basis. reduced to 10-bit crc in fail-over mode. b) the host computes check bits for (write) data - 22-bit crc on a per 72-bit write burst basis. reduced to 10- bit crc in fail-over mode. c) the amb detects crc errors in southbound commands or (write) data, and logs information on the errors detected - command or write data errors once observed prevent the amb from decoding any commands except the d) soft channel reset comma nd or until the channel is reset by the host - the amb does not evaluate any ecc information sent with the (dram) write or attempt to correct any errors e) the amb returns error status on detected errors - crc errors are reported on the northbound link by inserting alert frames in place of other content. - alerts continue to be sent until a soft channel reset command is received or the channel is reset. northbound read data b fb-dimm supports three northbound crc modes to support applications that requi re different levels of error detection and cost. the frames contain two 72-bit or 64-bit data payloads. each data payload is protected by either a 12-bit crc or a 6-bit crc, with reduced protection during fail-over. the three supported northbound crc modes are: 14 bit lanes: 12-bit crc over 72-bit data payload, fail- over to 6-bit crc 13 bit lanes: 6-bit crc over 72-bit data payload, fail- over to ecc coverage only 12 bit lanes: 6-bit crc over 64-bit data payload, no fail- over the selection on the mode of operation is controlled by the host and communicated during the initialization process as defined in the initialization chapter. northbound crc is only computed for data frames. the idle, alert, and status frame types drive the upper bit lanes with a known data pattern. during fail-over the host ignores the missing bit lanes and operates with reduced crc coverage. a) the host detects an error in the data through crc (added by the amb when not in fail-over mode) or by ecc provided with the data when read from dram (provided by the host with the data when written to dram) - the host logs the information on errors detected - the host corrects the data if possible using the ecc included within the data - the host takes whatever other steps deemed prudent (such as reissuing the command to see if the data error was transient or scrubbing the dram location if it were a correctable error) northbound status b a) the amb computes a pari ty bit over its own status information b) the host detects an error in the northbound status return - the host logs the information on errors detected - the host takes whatever other steps deemed prudent (such as issuing another sync command ? up to a limit) - if there were no errors in the status return itself then the host would log any error information reported through the status return and take whatever other steps deemed prudent. as noted above, the host is the only agent that corrects errors in system data. however, to provide enhanced data integrity, the host may first retry a read request upon detecting a data error before
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram reliability, availabi lity and serviceability data sheet 48 rev. 1.10, 2005-11 02182005-fiin-vwua attempting to correct the error. furthermore, the host may choose to patrol memory, reading memory locations and writing back corrected data for any errors detected. such patrol ?scrubbing? is orthogonal to the fb-dimm error handling specif ication. it is left to the host designers to determine their own memory scrub methodology. the error logging done by the amb(s) and the host are designed to permit isolation of the error source. 10.4 error protection a nd detection methods 10.4.1 crc logic used on normal southbound frames see the amb buffer specification for details. 10.4.2 fail-over southbound frames fail-over southbound frames consist of 12 transfers of data delivered on the 9 southbound bit lanes. bit lane 9 is not available to carry crc bits in fail-over mode, and the crc code size is reduced in this mode. 10.4.3 write and read da ta ecc error protection fb-dimm makes provision for both read and write data to be protected with system defined ecc check bits per data block by supporting 8 check bits per 64 data bits in 14 and 13 lane northbound frames. the host generates the ecc code and passes it along with the write data to the amb. the amb will store the ecc along with the data in the dram memory . the amb will not check the ecc code for errors and the host may use whatever algorithm it chooses. this allows the host to use various complex ecc algorithms, possibly spread across multiple channels. the mapping of the data and ecc bits to the dram components and channel bit lanes can enhance the protection provided by the ecc code to cover dram device failures and channel bit lane failures. refer to the southbound command+wdata frame format and northbound data frame definitions for details. 10.5 southbound error handling at the amb errors in southbound frames are handled using the following method: a) check for crc errors in the command. if the amb detects an error in the command then discard the entire frame, and marks as faulted the commands or data from the previous frame. process as command error. log the error. the first crc error latches the error data contents. the amb will save the 72-bits plus crc bits from the previous frame and the command plus crc from the current frame. enter command error state: the amb is forced to discard [all] subsequent commands until the channel is reset. indicate error by returning alert frames. b) determine if the frame is a command, or command+wdata frame; evaluate each command within a frame separately. c) check if the command is a sync command. if sync then respond with status. d) check if the command is targeted for this amb then process command. if the command is an unrecognizable command then ignore the command. the amb is not expected to do dram protocol checking (e.g., looking for command conflicts such as a write interrupting a read, etc.) e) process the next command in the command frame if any are left. f) process next frame. 10.5.1 exiting command error state once an amb has entered the command error state it will no longer process comma nds other than the soft channel reset command. indication that the amb is in the command error state is made manifest by the hardware setting of the appropriate configuration register bit and returnin g alert frames. the amb will continue to operate in this mode until a soft channel
data sheet 49 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram reliability, availabi lity and serviceability reset command is received or the host resets the channel. 10.6 northbound error ha ndling at the amb the amb does not evaluate the data and/or ecc information provided to it by the dram in response to a read command; it will fo rward the information supplied by the dram unchanged with a crc for link error detection. an amb does not evaluate the data and/or ecc or crc information passing through it from ambs further south than it. 10.7 error logging refer to the amb bu ffer specification 10.8 fail-over mode operation during channel initializatio n each bit lane is tested to determine if it is functioning properly. if one of the southbound bit lanes, northbound bit lanes, or one bit lane in both directions is non-functional, the redundant bit lane(s) may be used to map out the bad bit lane. operation with the redundant bit lane used to map out a bad bit lane is described as ?fail-over mode.? 10.8.1 fail-over mode op eration on southbound lanes without the redundant bit lane used for crc protection on the southbound lanes, commands continue to be protected by the 10-bit compound checksum crc included with each command, dram write data continues to be protected by system level ecc data within the write data payload and the optional 12-bit crc across each 72-bit data block, and the configuration register write data (within a command+data frame) continues to be protected by a 10-bit compound checksum crc. 10.8.2 fail-over mode op eration on northbound lanes the 14-lane northbound frame provides a 12-bit crc over 72-bits of data in normal operation, and a 6- bit crc over 72-bits of data in fail-over mode. the 13-lane frames are without the redundant bit lane used for crc protection. the read data continues to be protected by system level ecc data withi n the read data payload, and the status res ponse continues to be covered by its 10-bit compound checksum crc. 10.9 amb pass-through functionality as noted earlier much of the discussion regarding amb behavior was from the viewpoint of having only a single amb on the channel. fb-dimm supports from one to eight dimms and several additional amb components per channel. as outlined in the protocol chapter, in terms of data movement an amb is responsible for: - receiving southbound frames from the host or another amb and in general re-driving those frames to a more southerly amb. - evaluating southbound frames for commands or data targeted to that amb and for checking all commands and data for errors. - receiving northbound frames from another amb (generally) and re-driving those frames to another northerly amb or to the host. - supplying frame content for read and status responses. each amb must maintain the compound checksums used on the southbound channel. as can be seen from the four simple steps above an amb does not check [for errors in] fr ames moving north that have been forwarded by another amb, the frames are either discarded and replaced by frames from this amb (if it is responsible for providing a re ad response), selectively overwritten by this amb (if this amb is providing a status response), or simply forwarded on to the next amb or host. because an amb component does not evaluate data passing northbound through it, a read response or idle frame being delivered by a more southerly amb at the same ti me as this amb is simply discarded without error notification. if a given amb is the last amb (southern most amb) it does not receive frames from the south and thus does not forward such
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram reliability, availabi lity and serviceability data sheet 50 rev. 1.10, 2005-11 02182005-fiin-vwua frames in the northerly dire ction. it is responsible, however, for always generating idle frames whenever it is not providing a read re sponse or status response frame in response to a command from the host. these frames enable easy error detection by the host whenever a read return or status return is not provided by an amb as scheduled by the host. particular attention is paid to the re liability of the pass-through logic. the logic is isolated from the rest of the internal amb functions to ensure that the pass-through mechanism is functional ev en if other amb functions have failed. this improves th e reliability of the channel by minimizing the amount of logic that could result in a single point of failure. 10.10 memory initialization the amb contains a memory built-in self-test (membist) engine that is used to test the dram devices on the dimm and initialize the contents of the dram devices to a known state. refer to the fbd dfx specification for details. 10.11 thermal trip sensor the amb is outfitted with a thermal sensor that measures the temperature of the amb die. a dac and comparator mechanism driven from a finite state machine in the amb periodi cally adjusts its value to indicate the temperature of the die. the temperature of the amb die can be read at any time in the thermal sensor register. the thermal trip registers can be set to signal thermal warnings whenever the value of the thermal sensor register is higher than the thermal trip register trip points. the amb provides the warning via bits in the status response that indicates if the thermal condition has been exceeded. refer to the amb buffer specification for details. seri al presence detect codes for fb-dimm modules
data sheet 51 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes 11 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect . all values with xx in the table are module specific byte s which are defined during production. list of spd code tables ? table 17 ?spd codes for pc2?4200f?444, table 1? on page 51 ? table 18 ?spd codes for pc2?4200f?444, table 2? on page 56 table 17 spd codes for pc2?4200f?444, table 1 product type hys72t128001hfn?3.7?a hys72t128001hfa?3.7?a organization 1 gbyte 1 gbyte 72 72 1 rank ( 8) 1 rank ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex 0 spd size crc / total / used 92 92 1 spd revision 10 10 2 key byte / dram device type 09 09 3 voltage level of this assembly 12 12 4 sdram addressing 45 45 5 module physical attributes 23 23 6 module type 07 07 7 module organization 09 09 8 fine timebase (ftb) dividend and divisor 00 00 9 medium timebase (mtb) dividend 01 01 10 medium timebase (mtb) divisor 04 04 11 t ck.min (min. sdram cycle time) 0f 0f 12 t ck.max (max. sdram cycle time) 20 20 13 cas latencies supported 33 33 14 t cas.min (min. cas latency time) 3c 3c 15 write recovery values supported (wr) 32 32 16 t wr.min (write recovery time) 3c 3c 17 write latency times supported 72 72 18 additive latency times supported 50 50
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes data sheet 52 rev. 1.10, 2005-11 02182005-fiin-vwua 19 t rcd.min (min. ras# to cas# delay) 3c 3c 20 t rrd.min (min. row active to row active delay) 1e 1e 21 t rp.min (min. row precharge time) 3c 3c 22 t ras and t rc extension 00 00 23 t ras.min (min. active to precharge time) b4 b4 24 t rc.min (min. active to active / refresh time) f0 f0 25 t rfc.min lsb (min. refresh recovery time delay) fe fe 26 t rfc.min msb (min. refresh recovery time delay) 01 01 27 t wtr.min (min. internal write to read cmd delay) 1e 1e 28 t rtp.min (min. internal read to precharge cmd delay) 1e 1e 29 burst lengths supported 03 03 30 terminations supported 07 07 31 drive strength supported 01 01 32 t refi (avg. sdram refresh period) c2 c2 33 t case.max delta / ? t 4r4w delta 51 51 34 psi(t-a) dram 60 60 35 ? t 0 (dt0) dram 34 34 36 ? t 2q (dt2q) dram 1d 1d 37 ? t 2p (dt2p) dram 23 23 38 ? t 3n (dt3n) dram 1e 1e 39 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) dram 43 43 40 ? t 5b (dt5b) dram 22 22 41 ? t 7 (dt7) dram 2a 2a 42 - 80 not used 00 00 81 channel protocols supported lsb 02 02 82 channel protocols supported msb 00 00 83 back-to-back access turnaround time 25 25 table 17 spd codes for pc2?4200f?444, table 1 (cont?d) product type hys72t128001hfn?3.7?a hys72t128001hfa?3.7?a organization 1 gbyte 1 gbyte 72 72 1 rank ( 8) 1 rank ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
data sheet 53 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes 84 amb read access delay for ddr2-800 56 44 85 amb read access delay for ddr2-667 44 38 86 amb read access delay for ddr2-533 3a 32 87 psi(t-a) amb 30 28 88 ? t idle_0 (dt idle_0) amb 35 39 89 ? t idle_1 (dt idle_1) amb 4d 53 90 ? t idle_2 (dt idle_2) amb 47 4e 91 ? t active_1 (dt active_1) amb 62 61 92 ? t active_2 (dt active_2) amb 4d 53 93 ? t l0s (dt l0s) amb 00 00 94 - 100 not used 00 00 101 amb personality bytes: pre-initialization (1) c0 10 102 amb personality bytes: pre-initialization (2) 00 48 103 amb personality bytes: pre-initialization (3) 00 00 104 amb personality bytes: pre-initialization (4) 44 00 105 amb personality bytes: pre-initialization (5) 00 00 106 amb personality bytes: pre-initialization (6) 00 08 107 amb personality bytes: post-initialization (1) 40 1a 108 amb personality bytes: post-initialization (2) 43 40 109 amb personality bytes: post-initialization (3) 00 00 110 amb personality bytes: post-initialization (4) 00 04 111 amb personality bytes: post-initialization (5) 6d 22 112 amb personality bytes: post-initialization (6) 04 00 113 amb personality bytes: post-initialization (7) 00 00 114 amb personality bytes: post-initialization (8) 05 00 115 amb manufacturers jedec id code lsb 80 80 116 amb manufacturers jedec id code msb 89 10 table 17 spd codes for pc2?4200f?444, table 1 (cont?d) product type hys72t128001hfn?3.7?a hys72t128001hfa?3.7?a organization 1 gbyte 1 gbyte 72 72 1 rank ( 8) 1 rank ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes data sheet 54 rev. 1.10, 2005-11 02182005-fiin-vwua 117 dimm manufacturers jedec id code lsb 80 80 118 dimm manufacturers jedec id code msb c1 c1 119 module manufacturing location xx xx 120 module manufacturing date year xx xx 121 module manufacturing date week xx xx 122 - 125 module serial number xx xx 126 cyclical redundancy code lsb af 82 127 cyclical redundancy code msb e8 e3 128 module product type, char #1 37 37 129 module product type, char #2 32 32 130 module product type, char #3 54 54 131 module product type, char #4 31 31 132 module product type, char #5 32 32 133 module product type, char #6 38 38 134 module product type, char #7 30 30 135 module product type, char #8 30 30 136 module product type, char #9 31 31 137 module product type, char #10 48 48 138 module product type, char #11 46 46 139 module product type, char #12 4e 33 140 module product type, char #13 33 2e 141 module product type, char #14 2e 37 142 module product type, char #15 37 41 143 module product type, char #16 41 41 144 module product type, char #17 20 20 145 module product type, char #18 20 20 146 module revision code 0x 0x table 17 spd codes for pc2?4200f?444, table 1 (cont?d) product type hys72t128001hfn?3.7?a hys72t128001hfa?3.7?a organization 1 gbyte 1 gbyte 72 72 1 rank ( 8) 1 rank ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
data sheet 55 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes 147 test program revision code xx xx 148 dram manufacturers jedec id code lsb 80 80 149 dram manufacturers jedec id code msb c1 c1 150 informal amb content revision tag (msb) 00 00 151 informal amb content revision tag (lsb) 05 00 152 - 175 not used 00 00 176 - 255 blank for customer use ff ff table 17 spd codes for pc2?4200f?444, table 1 (cont?d) product type hys72t128001hfn?3.7?a hys72t128001hfa?3.7?a organization 1 gbyte 1 gbyte 72 72 1 rank ( 8) 1 rank ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes data sheet 56 rev. 1.10, 2005-11 02182005-fiin-vwua table 18 spd codes for pc2?4200f?444, table 2 product type hys72t256021hfn?3.7?a hys72t256021hfa?3.7?a organization 2 gbyte 2 gbyte 72 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex 0 spd size crc / total / used 92 92 1 spd revision 10 10 2 key byte / dram device type 09 09 3 voltage level of this assembly 12 12 4 sdram addressing 45 45 5 module physical attributes 23 23 6 module type 07 07 7 module organization 11 11 8 fine timebase (ftb) dividend and divisor 00 00 9 medium timebase (mtb) dividend 01 01 10 medium timebase (mtb) divisor 04 04 11 t ck.min (min. sdram cycle time) 0f 0f 12 t ck.max (max. sdram cycle time) 20 20 13 cas latencies supported 33 33 14 t cas.min (min. cas latency time) 3c 3c 15 write recovery values supported (wr) 32 32 16 t wr.min (write recovery time) 3c 3c 17 write latency times supported 72 72 18 additive latency times supported 50 50 19 t rcd.min (min. ras# to cas# delay) 3c 3c 20 t rrd.min (min. row active to row active delay) 1e 1e 21 t rp.min (min. row precharge time) 3c 3c 22 t ras and t rc extension 00 00 23 t ras.min (min. active to precharge time) b4 b4 24 t rc.min (min. active to active / refresh time) f0 f0 25 t rfc.min lsb (min. refresh recovery time delay) fe fe 26 t rfc.min msb (min. refresh recovery time delay) 01 01
data sheet 57 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes 27 t wtr.min (min. internal write to read cmd delay) 1e 1e 28 t rtp.min (min. internal read to precharge cmd delay) 1e 1e 29 burst lengths supported 03 03 30 terminations supported 07 07 31 drive strength supported 01 01 32 t refi (avg. sdram refresh period) c2 c2 33 t case.max delta / ? t 4r4w delta 51 51 34 psi(t-a) dram 60 60 35 ? t 0 (dt0) dram 34 34 36 ? t 2q (dt2q) dram 1d 1d 37 ? t 2p (dt2p) dram 23 23 38 ? t 3n (dt3n) dram 1e 1e 39 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) dram 43 43 40 ? t 5b (dt5b) dram 22 22 41 ? t 7 (dt7) dram 2a 2a 42 - 80 not used 00 00 81 channel protocols supported lsb 02 02 82 channel protocols supported msb 00 00 83 back-to-back access turnaround time 25 25 84 amb read access delay for ddr2-800 56 44 85 amb read access delay for ddr2-667 44 38 86 amb read access delay for ddr2-533 3a 32 87 psi(t-a) amb 30 28 88 ? t idle_0 (dt idle_0) amb 35 39 89 ? t idle_1 (dt idle_1) amb 4d 53 90 ? t idle_2 (dt idle_2) amb 47 4e 91 ? t active_1 (dt active_1) amb 62 61 table 18 spd codes for pc2?4200f?444, table 2 (cont?d) product type hys72t256021hfn?3.7?a hys72t256021hfa?3.7?a organization 2 gbyte 2 gbyte 72 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes data sheet 58 rev. 1.10, 2005-11 02182005-fiin-vwua 92 ? t active_2 (dt active_2) amb 4d 53 93 ? t l0s (dt l0s) amb 00 00 94 - 100 not used 00 00 101 amb personality bytes: pre-initialization (1) c0 10 102 amb personality bytes: pre-initialization (2) 00 48 103 amb personality bytes: pre-initialization (3) 00 00 104 amb personality bytes: pre-initialization (4) 44 00 105 amb personality bytes: pre-initialization (5) 00 00 106 amb personality bytes: pre-initialization (6) 00 08 107 amb personality bytes: post-initialization (1) 40 1a 108 amb personality bytes: post-initialization (2) 43 40 109 amb personality bytes: post-initialization (3) 00 00 110 amb personality bytes: post-initialization (4) 00 04 111 amb personality bytes: post-initialization (5) 6d 22 112 amb personality bytes: post-initialization (6) 04 00 113 amb personality bytes: post-initialization (7) 00 00 114 amb personality bytes: post-initialization (8) 05 00 115 amb manufacturers jedec id code lsb 80 80 116 amb manufacturers jedec id code msb 89 10 117 dimm manufacturers jedec id code lsb 80 80 118 dimm manufacturers jedec id code msb c1 c1 119 module manufacturing location xx xx 120 module manufacturing date year xx xx 121 module manufacturing date week xx xx 122 - 125 module serial number xx xx 126 cyclical redundancy code lsb c2 ef table 18 spd codes for pc2?4200f?444, table 2 (cont?d) product type hys72t256021hfn?3.7?a hys72t256021hfa?3.7?a organization 2 gbyte 2 gbyte 72 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
data sheet 59 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes 127 cyclical redundancy code msb 9d 96 128 module product type, char #1 37 37 129 module product type, char #2 32 32 130 module product type, char #3 54 54 131 module product type, char #4 32 32 132 module product type, char #5 35 35 133 module product type, char #6 36 36 134 module product type, char #7 30 30 135 module product type, char #8 32 32 136 module product type, char #9 31 31 137 module product type, char #10 48 48 138 module product type, char #11 46 46 139 module product type, char #12 4e 33 140 module product type, char #13 33 2e 141 module product type, char #14 2e 37 142 module product type, char #15 37 41 143 module product type, char #16 41 41 144 module product type, char #17 20 20 145 module product type, char #18 20 20 146 module revision code 0x 0x 147 test program revision code xx xx 148 dram manufacturers jedec id code lsb 80 80 149 dram manufacturers jedec id code msb c1 c1 150 informal amb content revision tag (msb) 00 00 151 informal amb content revision tag (lsb) 05 00 table 18 spd codes for pc2?4200f?444, table 2 (cont?d) product type hys72t256021hfn?3.7?a hys72t256021hfa?3.7?a organization 2 gbyte 2 gbyte 72 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram spd codes data sheet 60 rev. 1.10, 2005-11 02182005-fiin-vwua 152 - 175 not used 00 00 176 - 255 blank for customer use ff ff table 18 spd codes for pc2?4200f?444, table 2 (cont?d) product type hys72t256021hfn?3.7?a hys72t256021hfa?3.7?a organization 2 gbyte 2 gbyte 72 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
data sheet 61 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram package outline 12 package outline all components are surface mounted on one or both sides of the pcb and positioned on the pcb to meet the minimum and maximum trace lengths required for ddr2 sdram signals. bypass capacitors for ddr2 sdram devices are located near the device power pins. the amb device in th e center of the dimm has a metal heat spreader. the fb-dimm mechanical outlines are consistent with jedec mo-256. attention: heat spreader and clip heat up during oper ation. when unplugging a dimm from a system direct skin contact should be avoided until the heat spreader has reached room temperature. attention: the clip is mechanically loaded. do not remove. removal of the clip may cause injuries. attention: any mechanical stress on the heat spreader should be avoided. touching the heatspreader while plugging or unplugging the module may permanently damage the dimm. table 19 raw card reference jedec raw card infine on pcb dimensions width [mm] height [mm] thickness [mm] notes r/c a l-dim-240-21 figure 18 133.35 30.35 7.1 1) 1) thickness includes infineon heatspr eader. some early production modu les with jedec heatspreader may be thicker up to 8.2mm. r/c b l-dim-240-22 figure 19 133.35 30.35 7.1 1)
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram package outline data sheet 62 rev. 1.10, 2005-11 02182005-fiin-vwua figure 18 package outline l-dim-240-21 ! $ e t a i l o f c o n t a c t s " u r r m a x a l l o w e d - ) . ? ? " ! # # ? ? ? ? x " ! ? ? ? ? ? ? " ? ' , $ ? ? # ? - ! 8 - ! 8 - ! 8 - ! 8
data sheet 63 rev. 1.10, 2005-11 02182005-fiin-vwua hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram package outline figure 19 package outline l-dim-240-22 ' , $ ! " u r r m a x a l l o w e d $ e t a i l o f c o n t a c t s - ) . ? ? " ! # # ? ? ? ? x ! " ? ? ? ? ? ? " ? ? ? # ? - ! 8 - ! 8 - ! 8 - ! 8
hys72t[128/256]0[01/ 21]hf[n/a]?3.7 1-gbit ddr2 sdram ddr2 nomencature data sheet 64 rev. 1.10, 2005-11 02182005-fiin-vwua 13 ddr2 nomencature table 20 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys64t64128020km?5?a ddr2 dram hyb 18 t 5121g 16 0 a c ?5 table 21 ddr2 dimm nomenclature field description values coding 1infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered 10 speed grade ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. table 22 ddr2 dram nomenclature field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status cfbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3
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